EP80579 Datasheet, PDF (534/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.11 Offset 18h: PBUSN - Primary Bus Number Register
This register identifies that “virtual” PCI-to-PCI bridge is connected to bus 0.
Table 16-150.Offset 18h: PBUSN - Primary Bus Number Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 18h
Offset End: 18h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 18h
Offset End: 18h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
BUSN
Primary Bus Number: Configuration software typically
programs this field with the number of the bus on the
primary side of the bridge. Since Device 2 is an internal
device and its primary bus is always 0, these bits are
hardwired to 0.
Sticky
Bit Reset
Value
00h
Bit Access
RO
16.4.1.12 Offset 19h: SBUSN - Secondary Bus Number Register
This register identifies the bus number assigned to the second bus side of the “virtual”
PCI-to-PCI bridge (the PCI Express* connection). This number is programmed by the
PCI configuration software to allow mapping of configuration cycles to a second bridge
device connected to PCI Express*.
Table 16-151.Offset 19h: SBUSN - Secondary Bus Number Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 19h
Offset End: 19h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 19h
Offset End: 19h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
BUSN
Secondary Bus Number: This field is programmed by
configuration software with the lowest bus number of the
PCI Express* port.
Bit Reset
Value
00h
Bit Access
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
534
August 2009
Order Number: 320066-003US