EP80579 Datasheet, PDF (1088/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 27-35. Transitions Due to Power Button
Present
State
Event
S0/Cx PWRBTN# goes low
Transition/Action
SMI# or SCI generated
(depending on SCI_EN)
S1-S5 PWRBTN# goes low
Wake Event. Transitions to S0
state.
G3
PWRBTN# pressed
None
S0 -S4
PWRBTN# held low for at
least 4 consecutive
seconds
Unconditional transition to S5
state.
Comment
Software will typically initiate a
Sleep state.
Standard wakeup
Note: Could be impacted by
SLP_S4# minimum
assertion.
No effect since no power.
Not latched nor detected.
No dependence on processor (such
as Stop-Grant cycles) or any other
subsystem.
27.8.1.1
Power Button Override Function
If PWRBTN# is observed active for at least 4 consecutive seconds, then the state
machine must unconditionally transition to the G2/S5 state, regardless of present state
(S0-,S4) even if PWROK is not active. In this case, the transition to the G2/S5 state
must not depend on any particular response from the processor (such as a Stop-Grant
cycle), nor any similar dependency from any other subsystem.
Note:
The 4-second PWRBTN# assertion must only be used if a system lock-up has occurred.
The 4-second timer starts counting when CMI is in a S0 state. If the PWRBTN# signal is
asserted and held active when the system is in a suspend state (S1,S5), the assertion
causes a wake event. Once the system has resumed to the S0 state, the 4-second
timer starts. The PWRBTN# status is readable to check if the button is currently being
pressed or has been released. The status is taken after the debounce, and is readable
via the PWRBTN_LVL bit.
Note:
During the time that the SLP_S4# signal is stretched for the minimum assertion width
(if enabled by D31:F0:A4h bit 3), the Power Button is not a wake event. As a result, it
is conceivable that the user will press and continue to hold the Power Button waiting for
the system to awake. Since a 4-second press of the Power Button is already defined as
an Unconditional Power down, the power button timer will be forced to inactive while
the power-cycle timer is in progress. Once the power-cycle timer has expired, the
Power Button awakes the system. Once the minimum SLP_S4# power cycle expires,
the Power Button must be pressed for another 4 to 5 seconds to create the Override
condition to S5.
27.8.1.2
Sleep Button
The Advanced Configuration and Power Interface (ACPI) Specification, Rev. 2.0b
defines an optional Sleep button. It differs from the power button in that it only is a
request to go from S0 to S1-S4 (not S5). Also, in an S5 state, the Power Button can
wake the system, but the Sleep Button cannot.
Although CMI does not include a specific signal designated as a Sleep Button, one of
the GPIO signals can be used to create a “Control Method” Sleep Button See the ACPI
Specification for implementation details.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1088
August 2009
Order Number: 320066-003US