EP80579 Datasheet, PDF (1523/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.6.33 RNBC – Receive No Buffers Count Register
This register counts the number of times that frames were received when there were
no available buffers in host memory to store those frames (receive descriptor head and
tail pointers were equal). The packet will still be received if there is space in the FIFO.
This register does not increment when flow control packets are received. This register
will only increment if receives are enabled.
Table 37-111.RNBC: Receive No Buffers Count Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 40A0h
Offset End: 40A3h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 40A0h
Offset End: 40A3h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 40A0h
Offset End: 40A3h
Size: 32 bits
Default: 00000000h
Power
Well:
GbE0: Aux
Gbe1/2: Core
Bit Range Bit Acronym
Bit Description
31 : 00
RNBC
Number of receive no buffer conditions
Sticky
Bit Reset
Value
0h
Bit Access
RC
37.6.6.34 RUC – Receive Undersize Count Register
This register counts the number of received frames that passed address filtering, and
were less than minimum size (64B from <Destination Address> through <CRC>,
inclusively), and had a valid CRC. This register will only increment if receives are
enabled.
Table 37-112.RUC: Receive Undersize Count Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 40A4h
Offset End: 40A7h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 40A4h
Offset End: 40A7h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 40A4h
Offset End: 40A7h
Size: 32 bits
Default: 00000000h
Power
Well:
GbE0: Aux
Gbe1/2: Core
Bit Range Bit Acronym
Bit Description
31 : 00
RUC
Number of receive undersize errors
Sticky
Bit Reset
Value
0h
Bit Access
RC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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