EP80579 Datasheet, PDF (162/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 6-2.
Power Wells and External Voltages
Power
Well
Nominal
Voltage
Components
1.0-1.3 V
1.2 V
Core
Suspend
RTC
1.8 V
2.5 V
3.3 V
5.0V
1.2 V
2.5 V
3.3 V
5.0V
3.3 V
IA Processor: IA-CPU
Core Logic (IMCH, IICH, ASU, SSU, TDM, GbE MAC1, GbE MAC2), SATA pads, PCI-E
pads, Local Expansion Bus
PCI-E PLL, DDR2 pads. Note: 0.9V are generated from 1.8V
RMII/RGMII
SATA, PCI-E
5V tolerance reference
IICH, USB pads, DDR2 core logic, GbE MAC0, USB core logic and pads
RMII/RGMII
USB pads, RMII/RGMII pads
5V sustain reference
RTC
6.1.1.2
Hard Reset Implementation
A hard reset is initiated by the IICH via the PLTRST# as a result various S-state wake
events or other reset signal assertions. PLTRST# is driven to the IMCH and is
propagated from there to the reset block for AIOC fabric. The reset block in the AIOC
fabric is responsible for resetting the individual blocks.
IMCH propagates a hard reset to the FSB and subordinate PCI Express* subsystems.
The FSB components are reset via the CPURST# (internal signal) signal, while the PCI
Express* subsystems through PCIRST#.
6.1.1.3
Software Controlled Reset
Software may cause a full system reset through a write to the Reset Control Register
located at I/O port CF9. See also Section 6.1.1.4, “CPU Only Reset Implementation” for
software controlled CPU only reset mechanisms.
6.1.1.4
CPU Only Reset Implementation
For power management, error conditions and other reasons, the EP80579 supports a
targeted CPU only reset semantic. This mechanism eliminates system reset at large
when the CPU function (such as clock gearing selection) must be updated during
initialization. It only affects the IA-32 core. Other blocks such as IICH, IMCH, AIOC
complex are not reset. It is controlled by IMCH.
The IA-32 core can also be reset via the assertion of its INIT# pin which may be
accomplished by several conditions including a software write to the Reset Control
Register in IICH. Asserting the INIT# pin on the IA-32 core invokes a response similar
to that of asserting CPURST#. The major difference is that during an INIT, the internal
caches, MSRs, MTRRs, and FPU state are left unchanged (although, the TLBs and BTB
are invalidated as with a hardware reset). When INIT is signaled while the processor is
in virtual-8086 mode, the processor leaves virtual-8086 mode and enters real-address
mode. An INIT provides a method for switching from protected to real-address mode
while maintaining the contents of the internal caches.
Intel^® EP80579 Integrated Processor Product Line Datasheet
162
August 2009
Order Number: 320066-003US