EP80579 Datasheet, PDF (560/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.47 Offset 6Eh: PEADEVSTS - PCI Express* Device Status Register
This register provides information about PCI Express* device specific parameters.
Table 16-186.Offset 6Eh: PEADEVSTS - PCI Express Device Status Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 6Eh
Offset End: 6Fh
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 6Eh
Offset End: 6Fh
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 06
05
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
Reserved
TP
Reserved
URS
FED
NFED
CED
Reserved
Transactions Pending: Indicates that the device has
transactions pending.
0 = Cleared by hardware only when all pending
transactions (including completions for any
outstanding non-posted requests on any used virtual
channel) have been completed.
1 = Set by hardware to indicate that transactions are
pending (including completions for any outstanding
non-posted requests for all used Traffic Classes).
Reserved
Unsupported Request Detected: Indicates that an
Unsupported Request has been detected. This bit is set
upon Unsupported Request detection regardless of whether
or not error reporting is enabled in the Device Control
register. Software clears this bit by writing a ‘1’ to the bit
location.
0 = No Unsupported Request detected
1 = Unsupported Request detected
Fatal Error Detected: Indicates that a fatal error has
been detected. This bit is set upon fatal error detection
regardless of whether or not error reporting is enabled in
the Device Control register. Software clears this bit by
writing a ‘1’ to the bit location.
0 = No fatal error detected
1 = Fatal error detected
Non-fatal Error Detected: Indicates that a nonfatal error
has been detected. This bit is set upon nonfatal error
detection regardless of whether or not error reporting is
enabled in the Device Control register. Software clears this
bit by writing a ‘1’ to the bit location.
0 = No nonfatal error detected
1 = Nonfatal error detected
Correctable Error Detected: Indicates that a correctable
error has been detected. This bit is set upon correctable
error detection regardless of whether or not error reporting
is enabled in the Device Control register. Software clears
this bit by writing a ‘1’ to the bit location.
0 = No correctable error detected
1 = Correctable error detected
Bit Reset
Value
000h
0b
0b
0b
0b
0b
0b
Bit Access
RO
RWC
RWC
RWC
RWC
Intel^® EP80579 Integrated Processor Product Line Datasheet
560
August 2009
Order Number: 320066-003US