EP80579 Datasheet, PDF (1555/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.7.4.3 Transition from D0a to D3 and Back with Reset
Figure 37-54.Transition from D0a to D3 and Back with Reset
CLK
RESET
Reading EEPROM
1
tclkpr1
2
3
tprclk
4
tpree
tee
Read EEPROM
tprmem ⁸ _{Memory Access Enable 9}
Wakeup Enabled
DState
Any mode
D0a
tprwdis
Dr
7
APM
D0u
D0a
Note
1
2
4
6
10
11
Writing a 11 to the Power State field of the Power Management Control/Status Register (PMCSR)
will transition the MAC to D3.
The system can delay an arbitrary amount of time between setting D3 mode and asserting RESET.
Upon assertion of RESET the MAC will go to “Dr” state.
The deassertion edge of RESET will case the EEPROM to be re-read and Wake Up disabled.
The system can delay an arbitrary time before enabling memory access.
Writing a 1 to the Memory Access Enable bit in the PCI Command Register will transition the MAC
from D0u to D0 state.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1555