EP80579 Datasheet, PDF (872/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.3.4.6 Offset 134h: PxSACT[0-1] – Port [0-1] Serial ATA Active Register
Table 23-69. Offset 134h: PxSACT[0-1] – Port [0-1] Serial ATA Active Register
Description:
View: PCI
BAR: ABAR
Bus:Device:Function: 0:31:2
Offset Start: 134h, 1B4h
Offset End: 137h, 1B7h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 00
Bit Acronym
Bit Description
Sticky
Device Status (DS): System software sets this bit for
random queuing operations prior to setting the PxCI.CI bit
in the same command slot entry. This field is cleared via
DS
the Set Device Bits FIS.
This field is also cleared when PxCMD.ST is cleared by
software. Note that this field is not cleared by COMRESET
or SRST.
Bit Reset
Value
0h
Bit Access
RWS
23.3.4.7 Offset 138h: PxCI[0-1] – Port [0-1] Command Issue Register
Table 23-70. Offset 138h: PxCI[0-1] – Port [0-1] Command Issue Register
Description:
View: PCI
BAR: ABAR
Bus:Device:Function: 0:31:2
Offset Start: 138h, 1B8h
Offset End: 13Bh, 1BBh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 00
Bit Acronym
Bit Description
Sticky
Commands Issued (CI): This field is set by software to
indicate to the HBA that a command has been built in
system memory for a command slot and may be sent to
CI
the device. When the HBA receives a FIS which clears the
BSY, ERR, and DRQ bits for the command, it clears the
corresponding bit in this register for that command slot.
This field is also cleared when PxCMD.ST is written from a
‘1’ to a ‘0’ by software.
Bit Reset
Value
0h
Bit Access
RWS
Intel^® EP80579 Integrated Processor Product Line Datasheet
872
August 2009
Order Number: 320066-003US