EP80579 Datasheet, PDF (1087/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Note:
27.7.2
27.7.3
27.7.4
27.8
27.8.1
PROCHOT# assertion does not cause a TCO event message in S3 or S4. The level of the
signal is not reported in the heartbeat message.
Processor Passive Cooling
The FORCE_THTL bit allows the BIOS to force passive cooling independent of the ACPI
software (which uses the THTL_EN and THTL_DTY bits). It has the following behavior:
1. If this bit is set, CMI will start throttling using the ratio in the PROCHOT_DTY field.
2. If this bit is turned off, (cleared) CMI will stop throttling, unless the THTL_EN bit is
set (indicating that ACPI software is attempting throttling).
If both the THTL_EN and FORCE_THTL bits are both set, then the IICH must use the
duty cycle defined by the PROCHOT_DTY field, not the THTL_DTY field. (i.e.,
PROCHOT_DTY has higher priority).
On-Demand Passive Cooling
This is a method to cool the system by throttling the processor. The mode is initiated by
software setting the THTL_EN or THTL_DTY bits.
Behavioral Description:
1. Software sets the THTL_DTY bits to select throttle ratio and the THTL_EN bit to
enable the throttling.
2. Throttling results in STOPCLK# active for a minimum time of 12.5% and a
maximum of 87.5%. The period is 1024 PCI clocks. Thus, the STOPCLK# signal can
be active for as little as 128 PCI clocks or as much as 896 PCI clocks. The actual
slowdown (and cooling) of the processor will depend on the instruction stream,
because the processor is allowed to finish the current instruction. Furthermore, CMI
waits for the STOP-GRANT cycle before starting the count of the time the
STOPCLK# signal is active.
3. CMI will perform the Go-C2/Ack-C2 and Go-C0/Ack-C0 messages for throttling, just
as if it were making transitions to/from a C2 state.
Active Cooling
Active cooling involves fans. The GPIO signals from CMI can be used to turn on/off a
fan.
Event Input Signals, Messages and Their Usage
CMI has various input signals that trigger specific events. This section describes those
signals and how they should be used.
PWRBTN# – Power Button
CMI PWRBTN# signal operates as a “Fixed Power Button” as described in the ACPI
Specification. PWRBTN# signal has a 16 ms debounce on the input. The state transition
descriptions are included in Table 27-35. The transitions start as soon as the PWRBTN#
is pressed (but after the debounce logic), and does not depend on when the Power
Button is released. A power button override will force a transition to S5, even if PWROK
is not active.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1087