EP80579 Datasheet, PDF (53/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
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Transmit Descriptor (TDESC) Layout ..................................................................1366
Legacy Transmit Descriptor (TDESC) Layout .......................................................1366
Transmit Command (TDESC.CMD) Layout...........................................................1367
Transmit Status Layout (TDESC.STATUS) ...........................................................1368
Transmit Special Field Layout (TDESC.SPECIAL) ..................................................1369
TCP/IP Context Transmit Descriptor (TDESC) - (Type = 0000)...............................1370
TCP/IP Context Transmit Descriptor Command Field (TDESC.TUCMD).....................1371
TCP/IP Context Transmit Descriptor Status (TDESC.TUSTATUS).............................1372
TCP/IP Data Transmit Descriptor Layout (TDESC) - (Type = 0001).........................1373
TCP/IP Data Transmit Descriptor Command Field (TDESC.DCMD) ..........................1373
TCP/IP Data Transmit Descriptor Status (TDESC.DSTATUS) ..................................1375
TCP/IP Data Transmit Descriptor Packet Options Field (TDESC.POPTS) ...................1375
TCP/IP Data Transmit Descriptor Special Field (TDESC.VLAN) ................................1375
Transmit Descriptor Ring Structure ....................................................................1376
Transmit Descriptor and TUCMD Field (TDESC) Layouts - (Type = 0000) ................1380
TCP/IP Packet Format ......................................................................................1382
TCP/IP Context Transmit Descriptor & Command Layout.......................................1383
TCP Partial Pseudo-Header Checksum for IPv4 ....................................................1384
TCP Partial Pseudo-Header Checksum for IPv6 ....................................................1384
IPv4 Header (Traditional Representation) ...........................................................1385
IPv4 Header (Little-Endian Order)......................................................................1385
IPv6 Header (Traditional Representation) ...........................................................1385
TCP Header (Traditional Representation) ............................................................1386
TCP Header (Little-Endian Order) ......................................................................1386
TCP Pseudo Header Content (Traditional Representation)......................................1387
TCP Pseudo-Header Content for IPv6 .................................................................1387
UDP Header (Traditional Representation)............................................................1387
UDP Header (Little-Endian Order) ......................................................................1387
UDP Pseudo Header Diagram for IPv4 ................................................................1388
UDP Pseudo-Header Diagram for IPv6 ................................................................1388
Data Flow.......................................................................................................1391
802.3x MAC Control Frame Format ....................................................................1398
TCI Bit Ordering..............................................................................................1401
Memory Protection in the GbE ...........................................................................1419
Power State Transitions ...................................................................................1550
Reset Deasserted after 1st EEPROM Read Completes............................................1552
Reset Deasserted after before EEPROM Read Completes .......................................1553
Transition from D0a to D3 and Back without Reset...............................................1554
Transition from D0a to D3 and Back with Reset ...................................................1555
Reset without Transition to D3 ..........................................................................1556
CAN Block Diagram .........................................................................................1570
Standard CAN Data Frame................................................................................1572
Extended CAN Data Frame ...............................................................................1574
Standard CAN Remote Frame............................................................................1575
Extended CAN Remote Frame ...........................................................................1576
CAN Timing Parameters ...................................................................................1578
Bit Rate and Time Settings ...............................................................................1579
Receive Message Handler .................................................................................1581
Message Arbitration .........................................................................................1584
Programming Model.........................................................................................1621
Example Network Topology...............................................................................1623
Clock Synchronization ......................................................................................1625
Transparent Clock Switch Protocol Flow ..............................................................1627
Time Stamp Reference Point .............................................................................1632
Expansion Bus Controller..................................................................................1672
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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