EP80579 Datasheet, PDF (250/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 7-66. Bus M, Device 8, Function 0: Summary of Local Expansion Bus PCI
Configuration Registers (Sheet 2 of 2)
Offset Start Offset End
Register ID - Description
Default
Value
E7h
E7h
“Offset E7h: STYP: Signal Target Capability Type Register” on page 1330
01h
E8h
E8h
“Offset E8h: SMIA: Signal Target IA Mask Register” on page 1331
00h
ECh
ECh
“Offset ECh: SINT: Signal Target Raw Interrupt Register” on page 1331
00h
F0h
F0h
“Offset F0h: MCID: Message Signalled Interrupt Capability ID Register” on
page 1332
05h
F1h
F1h
“Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register” on
page 1332
00h
F2h
F3h
“Offset F2h: MCTL: Message Signalled Interrupt Control Register” on page 1333 0000h
F4h
F7h
“Offset F4h: MADR: Message Signalled Interrupt Address Register” on page 1333 00000000h
F8h
F9h
“Offset F8h: MDATA: Message Signalled Interrupt Data Register” on page 1334 0000h
Table 7-67. Bus M, Device 8, Function 0: Summary of Local Expansion Bus Registers
Mapped Through CSRBAR PCI Memory BAR"
Offset Start Offset End
Register ID - Description
00000000h 00000003h “EXP_TIMING_CS0 - Expansion Bus Timing Register” on page 1698
00000004h at
4h
00000007h at
4h
“EXP_TIMING_CS[1-7] - Expansion Bus Timing Registers” on page 1700
00000020h 00000020h “EXP_CNFG0 -Configuration Register 0” on page 1702
00000120h 00000123h “EXP_PARITY_STATUS - Expansion Bus Parity Status Register” on page 1703
Default
Value
BFFF3C40h
00000000h
00000040h
00000000h
§§
Intel^® EP80579 Integrated Processor Product Line Datasheet
250
August 2009
Order Number: 320066-003US