EP80579 Datasheet, PDF (386/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
15.3.5.2
15.3.6
15.3.6.1
While familiar and well understood, this mechanism does not provide for device-
initiated wake-up in the fully A/C coupled implementation of a multi-chassis PCI
Express-based system solution. The limitation imposed upon CMI-based system is that
remote-chassis devices must not be placed in a low-power state with the PCI Express
link clocking and/or power disabled if legacy style wake signaling is desired for any
peripheral in that remote chassis. It is still possible for software to place peripheral
devices in low power sleep states and to manage the device state of the PCI Express
device attached to the inter-chassis cable. Devices in the remote chassis may still
initiate power state changes via PME messaging provided the inter-chassis link has not
been placed into an uncommunicative state. An alternative for the platform architect
would be to place a compatible switch device between the IMCH and the remote chassis
that supports the in-band wake mechanism described below and rely on the switch to
forward wake events to the management controller.
The platform architect should ensure that the power management controller can
adequately isolate the source of a PME wake request as required to take appropriate
power management
wake-up action.
PME Messaging
Once the link requesting a power state change has a communicative upstream link, it
sends the PM_PME packet upstream toward the root device (IMCH), which in turn is
responsible for notifying the management controller. This constitutes an in-band
“virtual wire” signaling mechanism to replace the historical solution that involved
multiple independent board traces routing PME requests to the power manager.
Because the PM_PME propagates “in-band” on the PCI Express interface without any
side-band signaling support, PME functionality is made available to multi-chassis
system solutions.
The IMCH collects and “OR” PME requests from all logical PCI Express ports and
propagates it to IICH over the NSI link as an Assert_PMEGPE message. The IICH then
generates a specified interrupt to wake the power manager and invokes power
management software. The interrupt service routine may then interrogate the various
PM status registers to determine the source(s) of PME. The IMCH would send a
Deassert_PMEGPE message over NSI link after the power state change request has
been serviced.
BIOS Support for PCI Express PM Messaging
The PCI Express Specification stipulates hierarchical messaging semantics enforced by
the root device (IMCH) to guarantee proper entry into and exit from
unpowered device states. CMI ACPI BIOS must make special allowances for support of
these semantics. There are two sets of messages that must be software-assisted in CMI
based platforms to support power-off device states within the PCI Express hierarchy.
PCI Express PME_TURN_OFF Semantic
Prior to removing power from any attached PCI Express links anywhere in the
hierarchy, the root device must broadcast a PCI Express “PME_TURN_OFF” message to
all downstream devices on the affected PCI Express port. The receiving devices
propagate this message to all subordinate PCI Express ports (if any), collect
“PME_TO_ACK” acknowledgement packets, and finally return a “PME_TO_ACK”
transaction layer packet back to the root device. Once all active ports have
acknowledged, the power management device may be notified that it is cleared to
modify the collective power state of the PCI Express hierarchy. These message packets
have posted semantics on the interface, thus the turn-off “pushes” all prior packets to
Intel^® EP80579 Integrated Processor Product Line Datasheet
386
August 2009
Order Number: 320066-003US