EP80579 Datasheet, PDF (918/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
24.4
24.4.1
24.4.2
24.4.2.1
Host Controller
Overview
The SMB Host Controller is used to send commands to other SMB slave devices.
Software sets up the host controller with an address, command, and for writes, data
and optionally PEC; and then tells the controller to start. When the controller has
finished transmitting data on writes, or receiving data on reads, it generates an SMI#
or interrupt, if enabled.
The host controller supports eight command protocols of the SMB interface (see the
System Management Bus (SMBus) Specification, Version 2.0): Quick Command, Send
Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read, Block
Write and Block write-block read process call.
The SMB Host Controller requires that the various data and command fields be setup
for the type of command to be sent. When software sets the START bit, the SMB Host
Controller performs the requested transaction and interrupt the processor (or generate
an SMI#) when its finished. Once a START command has been issued, the values of the
“active registers” (Host Control, Host Command, Transmit Slave Address, Data0,
Data1) should not be changed or read until the interrupt status bit (INTR) has been set
(indicating the completion of the command). Any register values needed for
computation purposes should be saved prior to issuing of a new command, as the SMB
Host Controller will update all registers while completing the new command.
The CMI supports slave functionality, including the Host Notify protocol, on the SMLink
pins when in TCO compatible mode. Therefore, in order to be fully compliant with the
SMBus Specification (which requires the Host Notify cycle), the SMLink and SMBus
signals must be tied together externally.
Using the SMB Host Controller to send commands to the SMB slave port is not
supported.
Command Protocols
In all of the following commands, the Host Status Register (offset 00h) is used to
determine the progress of the command. While the command is in operation, the
HOST_BUSY bit is set. If the command completes successfully, the INTR bit is set in the
Host Status Register. If the device does not respond with an acknowledge, and the
transaction times out, the DEV_ERR bit is set. If software sets the KILL bit in the Host
Control Register while the command is running, the transaction stops and the FAILED
bit is set after the CMI forces a timeout. In addition, if the KILL bit is set during the CRC
cycle, both the CRCE and DEV_ERR bits are also set. When the KILL bit is set, the CMI
aborts current transaction by asserting SMBCLK low for greater than the timeout
period, asserts a STOP condition and then releases SMBCLK and SMBDATA. However,
setting the KILL bit does not affect SMLINK or TCO transactions or causes the CMI to
force a timeout if it is not performing a transaction.
Quick Command
When programmed for a quick command, the Transmit Slave Address Register is sent.
Table 24-31 shows the order. The PEC byte is never appended to the Quick Protocol.
Software must force the PEC_EN bit to ‘0’ when performing the Quick Command for
possible future enhancements. Also, Quick Command with I2C_EN set produces
undefined results. Software must force the I2C_EN bit to 0 when running this
command.
Intel^® EP80579 Integrated Processor Product Line Datasheet
918
August 2009
Order Number: 320066-003US