EP80579 Datasheet, PDF (275/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
10.1.6
CMI places the enhanced configuration aperture at E000_0000h by default, as this is
the first contiguous 256 MByte location below the 4 GByte boundary available for such
usage.
CMI provides for relocation of this aperture via the HECBASE register (see Section
16.1.1.35, “Offset CEh: HECBASE - PCI Express Port A (PEA) Enhanced Configuration
Base Address Register”, although validation of moving the region is minimal.
IOAPIC Memory Space
Table 10-8. IOAPIC Memory Space
From
IOAPIC0 (NSI)
0_FEC0_0000
IOAPIC2 (PEA0)
0_FEC8_0000
IOAPIC3 (PEA1)
0_FEC8_1000
To
0_FEC7_FFFF
0_FEC8_0FFF
0_FEC8_1FFF
The IOAPIC spaces are used to communicate with IOAPIC interrupt controllers that
may be populated on NSI through PCI-Express port A (PEA). Since it is difficult to
relocate an interrupt controller using plug-and-play software, fixed address decode
regions have been allocated for them. Processor accesses to the IOAPIC0 region are
always sent to NSI. Processor accesses to the IOAPIC2 region are always sent to PEA.
These regions are subject to the APIC disable, which are cleared by BIOS after the
allocated regions have been reflected down to the base registers of APIC controllers
discovered during standard enumeration. Until this step of the initialization sequence
has been performed, accesses to these regions are treated as subtractive decode and
routed to NSI.
The IMCH does not support an IOAPIC range for the EDMA controller or the AIOC, since
there is no IOxAPIC device or corresponding register set integrated into the EDMA
controller or the AIOC.
10.1.7 FSB Interrupt Memory Space
Table 10-9. FSB Interrupt Memory Space
From
FSBINTR
0_FEE0_0000
To
0_FEEF_FFFF
The FSB Interrupt space is the address range used to deliver interrupts to the FSB. Any
device below AIOC, NSI or a PCI Express port may issue a Memory Write to
0FEEx_xxxxh. The IMCH will forward this Memory Write along with its associated data
to the FSB as a Message Signaled Interrupt (MSI) transaction. The IMCH terminates
the FSB transaction by asserting TRDY# and providing the response. This Memory
Write cycle does not go to DRAM.
Reads to this address range are aborted by the IMCH.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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