EP80579 Datasheet, PDF (915/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
24.3.1.8
Offset 08h: PEC: Packet Error Check Data Register
This register contains the 8-bit CRC value that is used as the Packet Error Check on
SMBus. For writes, this register is written by software prior to running the command.
For reads, this register is read by software after the read command is completed on
SMBus.
Table 24-26. Offset 08h: PEC: Packet Error Check Data Register
Description:
View: PCI
BAR: SM_BASE (IO)
Bus:Device:Function: 0:31:3
Offset Start: 08h
Offset End: 08h
Size: 8 bit
Default: 00h
Power Well: Resume
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
PEC_DATA
This 8-bit register is written with the SMBus PEC data
prior to a write transaction. For read transactions, the
PEC data is loaded from the SMBus into this register and
is then read by software. Software must ensure that the
INUSE_STS bit is properly maintained to avoid having
this field overwritten by a write transaction following a
read transaction.
Bit Reset
Value
00h
Bit Access
RW
24.3.1.9 Offset 0Ch: AUXS: Auxiliary Status Register
Table 24-27. Offset 0Ch: AUXS: Auxiliary Status Register
Description:
View: PCI
BAR: SM_BASE (IO)
Bus:Device:Function: 0:31:3
Offset Start: 0Ch
Offset End: 0Ch
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 02
01
Bit Acronym
Bit Description
Sticky
Reserved
STCO
Reserved
SMBus TCO mode: This is the status bit that reflects
the setting of legacy TCO mode vs. Advanced TCO
mode.
0 = Indicates that this bit is always zero, since
Advanced TCO mode is not supported.
Bit Reset
Value
0h
0h
Bit Access
RO
CRC Error:
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set if a received message contained a
CRC error. When this bit is set, the DERR bit of the
00
CRCE
host status register is also set. This bit is set by the
controller if a software abort occurs in the middle of
the CRC portion of the cycle or an abort happens
after the CMI has received the final data bit
transmitted by an external slave.
0h
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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