EP80579 Datasheet, PDF (406/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.1.1.22 Offset 5Eh: PAM5 - Programmable Attribute Map 5 Register
This register controls the read, write, and shadowing attributes of the BIOS areas from
0E0000h-0E7FFFh.
Table 16-24. Offset 5Eh: PAM5 - Programmable Attribute Map 5 Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 5Eh
Offset End: 5Eh
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 06
05 : 04
03 : 02
01 : 00
Bit Acronym
Bit Description
Sticky
Reserved
HIENABLE
Reserved
LOENABLE
Reserved
Attribute Register 0E4000-0E7FFF: This field controls
the steering of read and write cycles that address the BIOS
area from 0E4000 to 0E7FFF.
Encoding Description
00
DRAM Disabled - All accesses are directed
to NSI.
01
Read-Only - All reads are serviced by DRAM.
All writes are forwarded to NSI.
10
Write Only - All writes are sent to DRAM.
Reads are serviced by NSI.
11
Normal DRAM Operation - All reads and
writes are serviced by DRAM.
Reserved
Attribute Register 0E0000-0E3FFF: This field controls
the steering of read and write cycles that address the BIOS
area from 0E0000 to 0E3FFF.
Encoding Description
00
DRAM Disabled - All accesses are directed
to NSI.
01
Read-Only - All reads are serviced by DRAM.
All writes are forwarded to NSI.
10
Write Only - All writes are sent to DRAM.
Reads are serviced by NSI.
11
Normal DRAM Operation - All reads and
writes are serviced by DRAM.
Bit Reset
Value
00b
00b
00b
00b
Bit Access
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
406
August 2009
Order Number: 320066-003US