EP80579 Datasheet, PDF (612/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-234.Offset 98h: DSRETC - DRAM Self-Refresh (SR) Extended Timing and Control
Register
Description: DSRETC: DRAM Self-Refresh (SR) Extended Timing and Control Register
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: 98h
Offset End: 9Bh
Size: 32 bit
Default: 5c141400h
Power Well: Core
Bit Range
15 :08
7 :1
00
Bit Acronym
Bit Description
Sticky
DRARTIM
Dual rank auto-refresh timing - stagger of commands
between ranks prior to self-refresh entry.
Y
Reserved Reserved
N
Enable Self-refresh (SR) exit state machine.
ENSREXIT _{This bit needs to be set by BIOS upon power-up from an}
N
S3 event.
Bit Reset
Value
00010100b
0000000b
0b
Bit Access
RW
RO
RW
16.5.1.8
Offset 9Ch: DQSFAIL1 - DQSFAIL1 Configuration Register
There are two DQSFAIL registers that contain a total of 18 individual DQS failure status
bits. There is one status bit for each DQS on each rank. These bits are set automatically
by hardware during the receiver enable calibration if a valid DQS waveform is not
detected. Hardware will not clear any bits that are set prior to the calibration even if a
valid waveform is detected.
Hardware uses the DQSFAIL information to exclude calibration data during the data
gathering portion and/or the data analysis portion of the both the receiver enable and
DQS delay calibrations as well as MBIST. This prevents a failed DQS pin from corrupting
the calibration of neighboring functional DQS pins that may share internal logic
resources with a failing DQS pin.
For normal calibration, initialize all DQSFAIL bits to 0.
Table 16-235.Offset 9Ch: DQSFAIL1 - DQS Failure Configuration Register 1
Description: DQSFAIL1: DQS Failure Configuration Register
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: 9Ch
Offset End: 9Ch
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range Bit Acronym
07 :04
03 03
02 02
01 01
00 00
Reserved Reserved
Reserved_R1DQ
S17
Reserved
R1DQS08 Rank 1 DQS08
Reserved_R1DQ
S16
Reserved
R1DQS07 Rank 1 DQS07
Bit Description
Sticky
N
Y
Y
Y
Y
Bit Reset
Value
0h
0b
0b
0b
0b
Bit Access
RO
RW
RW
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
612
August 2009
Order Number: 320066-003US