EP80579 Datasheet, PDF (1520/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.6.29 GORCL – Good Octets Received Count Low Register
This is the low 32b of a register that counts the number of octets received which are
associated with good packets (no link or CRC errors, no flow-control packets). This
counter is incremented for each good regular packet received to the Receive Packet
Buffer. Regular packets dropped due to Receive Packet Buffer overruns or due to the
driver's receiver being disabled are not included in this count. {GORCH,GORCL}
together make up a logical 64-bit register. Each half must be accessed independently
using separate 32-bit accesses. Both registers are reset when the upper 32-bit value
(GORCH) is read. The register sticks at 0xFFFF_FFFF_FFFF_FFFF.
Table 37-107.GORCL: Good Octets Received Count Low Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 4088h
Offset End: 408Ah
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 4088h
Offset End: 408Ah
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 4088h
Offset End: 408Ah
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
Bit Description
31 : 00
GORCL
Number of good octets received - lower 4 bytes
Sticky
Bit Reset
Value
0h
Bit Access
RC
Intel^® EP80579 Integrated Processor Product Line Datasheet
1520
August 2009
Order Number: 320066-003US