EP80579 Datasheet, PDF (21/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
20.2.1.3 Offset 01h: DMA_BCC[0-3] - DMA Base and Current Count Registers for
Channels 0-3 ................................................................................. 768
20.2.1.4 Offset C6h: DMA_BCC[5-7] - DMA Base and Current Count Registers for
Channels 5-7 ................................................................................. 769
20.2.1.5 Offset 08h: DMA_COMMAND - DMA Command Register........................ 770
20.2.1.6 Offset 87h: DMA_MPL[0-3] - DMA Memory Low Page Registers for Channels
0-3 ............................................................................................... 771
20.2.1.7 Offset 8Bh: DMA_MPL[5-7] - DMA Memory Low Page Registers for Channels
5-7 ............................................................................................... 771
20.2.1.8 Offset 08h: DMA_STATUS - DMA Status Register ................................ 772
20.2.1.9 Offset 0Ah: DMA_WSM - DMA Write Single Mask Register .................... 773
20.2.1.10 Offset 0Bh: DMA_CHM - DMA Channel Mode Register .......................... 774
20.2.1.11 Offset 0Ch: DMA_CBP - DMA Clear Byte Pointer Register...................... 775
20.2.1.12 Offset 0Dh: DMA_MC - DMA Master Clear Register .............................. 775
20.2.1.13 Offset 0Eh: DMA_CM - DMA Clear Mask Register ................................. 776
20.2.1.14 Offset 0Fh: DMA_WAM - DMA Write All Mask Register .......................... 777
20.3 DMA Channel Arbitration .................................................................................. 778
20.4 Special Cases in Address/Count......................................................................... 779
20.4.1 Address Overrun/Underrun ...................................................................... 779
20.4.2 16-Bit Channels ..................................................................................... 779
20.4.3 Autoinitialize ......................................................................................... 779
20.4.4 Software Commands .............................................................................. 779
20.5 Theory of Operation for LPC DMA....................................................................... 780
20.5.1 Asserting DMA Requests ......................................................................... 780
20.5.2 Abandoning DMA Requests ...................................................................... 780
20.5.3 General Flow of DMA Transfers ................................................................ 781
20.5.4 Terminal Count ...................................................................................... 781
20.5.5 Verify Mode ........................................................................................... 782
20.5.6 DMA Request Deassertion ....................................................................... 782
20.5.7 SYNC Field/LDRQ# Rules......................................................................... 783
21.0 Serial Peripheral Interface .................................................................................... 785
21.1 Overview ....................................................................................................... 785
21.1.1 Features ............................................................................................... 785
21.2 External Interface ........................................................................................... 785
21.3 SPI Protocol.................................................................................................... 786
21.3.1 SPI Pin-Level Protocol ............................................................................. 786
21.3.1.1
21.3.1.2
21.3.1.3
21.3.1.4
21.3.1.5
Addressing..................................................................................... 787
Data Transaction ............................................................................ 787
Bus Errors .................................................................................... 788
Instructions ................................................................................... 788
SPI Timings ................................................................................... 789
21.4 Host Side Interface.......................................................................................... 789
21.4.1 SPI Host Interface Registers .................................................................... 789
21.4.2 Register Overview .................................................................................. 789
21.4.2.1
21.4.2.2
21.4.2.3
21.4.2.4
21.4.2.5
21.4.2.6
21.4.2.7
21.4.2.8
21.4.2.9
21.4.2.10
Offset 3020h: SPIS – SPI Status ....................................................... 790
Offset 3022h: SPIC – SPI Control...................................................... 791
Offset 3024h: SPIA – SPI Address ..................................................... 792
Offset 3028h: SPID0 – SPI Data 0..................................................... 792
SPID[0-6] – SPI Data N ................................................................... 793
Offset 3070h: BBAR – BIOS Base Address .......................................... 793
Offset 3074h: PREOP – Prefix Opcode Configuration ............................ 794
Offset 3076h: OPTYPE – Opcode Type Configuration ............................ 794
Offset 3078h: OPMENU – Opcode Menu Configuration .......................... 795
Offset 3080h: PBR0 – Protected BIOS Range [0-2] .............................. 796
21.4.3 Running SPI Cycles from the Host ............................................................ 797
21.4.3.1 Memory Reads ............................................................................... 797
21.4.3.2 Generic Programmed Commands ...................................................... 799
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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