EP80579 Datasheet, PDF (829/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.1.2.1
Offset 40h: PTIM – Primary Timing Register
This controls the timings driven on the parallel cable.
Table 23-20. Offset 40h: PTIM – Primary Timing Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: 40h
Offset End: 41h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15
14
13 : 12
11 : 10
09 : 08
07
06
05
04
03
Bit Acronym
Bit Description
Sticky
DE
D1STE
ISP
Reserved
RCT
DTE1
PPE1
E1
TIM1
DTE0
Decode Enable (DE): Enables the SATA Controller to
decode the Command Blocks (1F0-1F7h for primary, 170-
177h for secondary or their native BAR equivalents) and
Control Block (3F6h for primary and 376h for secondary or
their native BAR equivalents). This bit still has
functionality in SATA – if this bit is not set, the port that is
mapped to this range will not be decoded.
Device 1 Separate Timing Enable (D1STE): When
cleared, both device 0 and device 1 use the same timings,
as defined by bits 13:12 and bits 9:8 of this register.
When set, device 0 uses these timings, but device 1 uses
the timings from the “Slave Timing” register at offset 44h.
IORDY Sample Point (ISP): Determines the number of
33 MHz clocks between IDE IOR#/IOW# assertion and the
first IORDY sample point.
00 = 5 clocks
01 = 4 clocks
10 = 3 clocks
11 = Reserved
Reserved
Recovery Time (RCT): The setting of these bits
determines the minimum number of 33 MHz clocks
between the last IORDY sample point and the IOR#/IOW#
strobe of the next cycle.
00 = 4 clocks
01 = 3 clocks
10 = 2 clocks
11 = 1 clock
Device 1 DMA Timing Enable (DTE1): When this bit is
set, the fast timing mode is enabled for DMA transfers
only for this drive. PIO transfers to the data port will run in
compatible timing.
Device 1 Prefetch/Posting Enable (PPE1): When this
bit is set, prefetch and posting to the IDE data port is
enabled for this drive.
Device 1 IORDY Sample Point Enable (IE1): When
this bit is set, IORDY sampling will be enabled for this
drive. When this bit is cleared, IORDY sampling is disabled
for this drive.
Device 1 Fast Timing Bank (TIM1): When cleared,
accesses to the data port will use compatible timings for
this drive. When set and bit 14 cleared, accesses to the
data port will use bits 13:12 for the IORDY sample point,
and bits 9:8 for the recovery time. When set and bit 14
set, accesses to the data port will use the IORDY sample
point and recover time specified in the slave IDE timing
register.
Device 0 DMA Timing Enable (DTE0): When this bit is
set, the fast timing mode is enabled for DMA transfers
only for this drive. PIO transfers to the IDE data port will
run in compatible timing.
Bit Reset
Value
0h
0h
00h
00h
00h
0h
0h
0h
0h
0h
Bit Access
RW
RW
RW
RO
RW
RW
RW
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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