EP80579 Datasheet, PDF (1118/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 30-4. 8259 Core Connection (Sheet 2 of 2)
8259
Slave
8259 Input
0
1
2
3
4
5
6
7
Typical Interrupt Source
Connected Pin / Function
Real Time Clock
Generic
Generic
Generic
PS/2 Mouse
Internal
SATA
SATA
Inverted IRQ8# from internal RTC or Multimedia
Timer 1
IRQ9 via SERIRQ, SCI, or TCO, PIRQx
IRQ10 via SERIRQ, SCI, or TCO, PIRQx
IRQ11 via SERIRQ, SCI, or TCO, PIRQx
IRQ12 via SERIRQ, SCI, or TCO, PIRQx
State Machine output based on processor FERR#
assertion. Can optionally be used for SCI or TCO
interrupts if FERR# is not needed.
SATA Primary (legacy mode), SERIRQ, PIRQx
SATA Secondary (legacy mode), SATA Secondary
(legacy mode), SERIRQ, PIRQx
The IICH cascades the slave controller onto the master controller through master
controller interrupt input 2. This means there are only 15 possible interrupts for the
IICH PIC.
Interrupts can individually be programmed to be edge or level, except for IRQ0, IRQ2,
IRQ8#.
Note:
Active-low interrupt sources, such as the PIRQ#s, are internally inverted in the IICH. In
the following descriptions of the 8259s, the interrupt levels are in reference to the
signals at the internal interface of the 8259s, after the required inversions have
occurred. Therefore, the term “high” indicates “active”, which means “low” on an
originating PIRQ#.
30.2.2
I/O Registers
The interrupt controller registers are located at 20h and 21h for the master controller
(IRQ0–7), and at A0h and A1h for the slave controller (IRQ8–13). These registers have
multiple functions depending upon the data written to them. Table 30-5 lists the
different register possibilities for each address.
Table 30-5. Summary of 8259 Interrupt Controller (PIC) Registers Mapped in I/O Space
Offset Start Offset End
Register ID - Description
Default
Value
020h, 0A0h
021h, 0A1h
21h
A1h
21h, 0A1h
021h, 0A1h
020h, 0A0h
020h, 0A0h
4D0h
4D1h
020h, 0A0h
021h, 0A1h
21h
A1h
21h, 0A1h
021h, 0A1h
020h, 0A0h
020h, 0A0h
4D0h
4D1h
“ICW1[0-1] - Initialization Command Word 1 Register” on page 1119
0001X0XXb
“ICW2[0-1] - Initialization Command Word 2 Register” on page 1120
XXh
“MICW3 - Master Initialization Command Word 3 Register” on page 1121
04h
“SICW3 - Slave Initialization Command Word 3 Register” on page 1121
00h
“ICW4[0-1] - Initialization Command Word 4 Register” on page 1122
01h
“OCW1[0-1]- Operational Control Word 1 (Interrupt Mask) Register” on page 1122 00h
“OCW2[0-1] - Operational Control Word 2 Register” on page 1123
001XXXXXb
“OCW3[0-1] - Operational Control Word 3 Register” on page 1124
001XX10b
“ELCR1 - Master Edge/Level Control Register” on page 1125
00h
“ELCR2 - Slave Edge/Level Control Register” on page 1126
00
Intel^® EP80579 Integrated Processor Product Line Datasheet
1118
August 2009
Order Number: 320066-003US