EP80579 Datasheet, PDF (536/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.15 Offset 1Dh: IOLIMIT - I/O Limit Address Register
This register controls the CPU to PCI Express* I/O access routing based on the
following formula:
IO_BASE =< address =< IO_LIMIT
Only the upper four bits are programmable. For the purpose of address decode address
bits A[11:00] are assumed to be FFFh. Thus, the top of the defined I/O address range
is at the top of a 4 Kbyte aligned address block.
Table 16-154.Offset 1Dh: IOLIMIT - I/O Limit Address Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 1Dh
Offset End: 1Dh
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 1Dh
Offset End: 1Dh
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 04
03 : 00
Bit Acronym
Bit Description
Sticky
IOLIMT
IOLM
I/O Address Limit: Corresponds to A[15:12] of the I/O
address limit of device. Devices between this upper limit
and IOBASE2 are passed to PCI Express*.
I/O Addressing mode: These bits are hardwired to 0.
0h = 16-bit I/O addressing
All other bit combinations are not supported.
Bit Reset
Value
0h
0h
Bit Access
RW
RO
16.4.1.16 Offset 1Eh: SECSTS - Secondary Status Register
SECSTS is a 16-bit status register that reports the occurrence of error conditions
associated with the secondary side (e.g., PCI Express* side) of the “virtual” PCI-PCI
bridge embedded within IMCH.
Table 16-155.Offset 1Eh: SECSTS - Secondary Status Register (Sheet 1 of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 1Eh
Offset End: 1Fh
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 1Eh
Offset End: 1Fh
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15
Bit Acronym
Bit Description
Sticky
2DPE
Detected Parity Error: This bit is set by the PCI Express*
Port logic when the secondary side receives a poisoned
TLP, regardless of the state of the Parity Error Enable bit.
Software clears this bit by writing a ‘1’ to the bit location.
See the PCI Express* Interface Specification, Rev 1.0a for
details.
0 = No parity Error detected.
1 = Parity Error Detected (poisoned TLP received).
Bit Reset
Value
0b
Bit Access
RWC
Intel^® EP80579 Integrated Processor Product Line Datasheet
536
August 2009
Order Number: 320066-003US