EP80579 Datasheet, PDF (681/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-349.Offset 04h: NSIPVCCAP1 - NSI Port VC Capability Register 1 (Sheet 2 of 2)
Description:
View: PCI
BAR: NSIBAR
Bus:Device:Function: 0:0:0
Offset Start: 04h
Offset End: 07h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
06 : 04
03
02 : 00
Bit Acronym
Bit Description
Sticky
LPEVCC
Reserved
EVCC
Low Priority Extended VC Count: Indicates the
number of (extended) Virtual Channels in addition to
the default VC belonging to the low-priority VC (LPVC)
group that has the lowest priority with respect to other
VC resources in a strict-priority VC Arbitration.
The value of 0 in this field implies strict VC arbitration.
Reserved
Extended VC Count: Indicates the number of
(extended) Virtual Channels in addition to the default
VC supported by the device. The Private Virtual Channel
is not included in this count. Only VC0 is supported.
Bit Reset
Value
000b
0b
000b
Bit Access
RO
RO
16.7.1.3
Offset 08h: NSIPVCCAP2 - Port VC Capability Register 2
This register describes the configuration of PCI Express Virtual Channels associated
with this port.
Table 16-350.Offset 08h: NSIPVCCAP2 - Port VC Capability Register 2
Description:
View: PCI
BAR: NSIBAR
Bus:Device:Function: 0:0:0
Offset Start: 08h
Offset End: 0Bh
Size: 32 bit
Default: 00000001h
Power Well: Core
Bit Range
31 : 24
23 : 08
07 : 00
Bit Acronym
Bit Description
Sticky
Reserved
Reserved
VCARBC
Reserved
Reserved
VC Arbitration Capability: Indicates that the only
possible VC arbitration scheme is hardware fixed (in the
root complex).
Bit Reset
Value
00h
0000h
01h
Bit Access
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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