EP80579 Datasheet, PDF (1307/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 35-123.Offset 04h: PCICMD: Device Command Register (Sheet 2 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:7:0
Offset Start: 04h
Offset End: 05h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
07
06
05
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
Reserved
PER
VPS
MWE
SS
BM
MEM
IO
Reserved
Parity Error Response
VGA Palette Snoop
Memory Write and Invalidate
Special Cycle
Bus Master Capable
Memory Space Enable: Setting this bit enables access to
the memory regions the device claims through its BARs.
I/O Space Enable: The device does not implement this
functionality since it claims no I/O regions. The bit is
hardwired to 0.
Bit Reset
Value
0h
0h
0h
0h
0h
0h
0h
0h
Bit Access
RV
RO
RO
RO
RO
RO
RW
RO
35.11.1.4 Offset 06h: PCISTS – Device Status Register
Table 35-124.Offset 06h: PCISTS: PCI Device Status Register (Sheet 1 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:7:0
Offset Start: 06h
Offset End: 07h
Size: 16 bit
Default: 0010h
Power Well: Core
Bit Range
15
14
13
12
11
10 : 09
08
07
06
Bit Acronym
Bit Description
Sticky
DPE
SSE
RMA
RTA
STA
DST
MDPE
FB2B
Reserved
Detected Parity Error: The device does not implement
this functionality. The bit is hardwired to 0. The EP80579
uses signals for errors.
Signaled System Error: The device does not implement
this functionality. The bit is hardwired to 0.
Received Master Abort Status: The device does not
implement this functionality. The bit is hardwired to 0.
Received Target Abort Status: The device does not
implement this functionality. The bit is hardwired to 0.
Signaled Target Abort Status: The device does not
implement this functionality. The bit is hardwired to 0.
DEVSEL Timing: The device does not implement this
functionality. These bits are hardwired to 0.
Master Data Parity Error Detected: The device does not
implement this functionality. The bit is hardwired to 0. The
EP80579 uses signals for errors.
Fast Back-to-Back Capable: The device does not
implement this functionality. The bit is hardwired to 0.
Reserved
Bit Reset
Value
0h
0h
0h
0h
0h
00b
0h
0h
0h
Bit Access
RO
RO
RO
RO
RO
RO
RO
RO
RV
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1307