EP80579 Datasheet, PDF (998/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 26-31. Offset 70h: ISU2SMI - Intel Specific USB 2.0 SMI Register (Sheet 2 of 3)
Description: Lockable: Suspend well, and not D3-to-D0 warm reset nor core well.
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 70h
Offset End: 73h
Size: 32 bit
Default: 00000000h
Power Well: Suspend
Bit Range
21
20
19
18
17
16
15 :14
13 :08
07 :06
05
04
03
Bit Acronym
Bit Description
Sticky
SMI_
PMCSR
SMI on PMCSR:
0 = Power State bits not modified.
1 = Software modified the Power State bits in the Power
Management Control/Status (PMCSR) register
(D29:F7:54h).
SMI_ASYNC
SMI on Async:
0 = No Async Schedule Enable bit change
1 = Async Schedule Enable bit transitioned from 1 to 0 or
0 to 1.
SMI_PER
SMI on Periodic:
0 = No Periodic Schedule Enable bit change.
1 = Periodic Schedule Enable bit transitions from 1 to 0 or
0 to 1.
SMI_CF
SMI on CF:
0 = No Configure Flag (CF) change.
1 = Configure Flag (CF) transitions from 1 to 0 or 0 to 1.
SMI_HCH
SMI on HCHalted:
0 = HCHalted did not transition to 1 (as a result of the
Run/Stop bit being cleared).
1 = HCHalted transitions to 1 (as a result of the Run/Stop
bit being cleared).
SMI_HCR
SMI on HCReset:
0 = HCRESET did not transition to 1.
1 = HCRESET transitioned to 1.
Reserved Reserved.
Reserved Reserved
SMI_POEN
SMI on PortOwner Enable: When any of these bits are
‘1’ and the corresponding SMI on PortOwner bits are ‘1’,
then the host controller will issue an SMI. Unused ports
must have their corresponding bits cleared.
SMI on PMSCR Enable:
SMI_PMSCREN
0=
1=
Disable.
Enable. When this bit is 1 and SMI on PMSCR is 1,
then the host controller will issue an SMI.
SMI_ASYEN
SMI on Async Enable:
0 = Disable.
1 = Enable. When this bit is 1 and SMI on Async is 1, then
the host controller will issue an SMI.
SMI_PEREN
SMI on Periodic Enable:
0 = Disable.
1 = Enable. When this bit is 1 and SMI on Periodic is 1,
then the host controller will issue an SMI.
Bit Reset
Value
0b
0b
0b
0b
0b
0h
00b
000000b
00b
0b
0b
0b
Bit Access
RWC
RWC
RWC
RWC
RWC
RWC
RW
RW
RW
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
998
August 2009
Order Number: 320066-003US