EP80579 Datasheet, PDF (1501/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 37-76. TXDCTL: Transmit Descriptor Control Register (Sheet 2 of 2)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 3828h
Offset End: 382Bh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 3828h
Offset End: 382Bh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 3828h
Offset End: 382Bh
Size: 32 bits
Default: 00000000h
GbE0: Core
Power Well: Gbe1/2:
Core
Bit Range
21 : 16
15 : 14
13 : 08
07 : 06
05 : 00
Bit Acronym
Bit Description
Sticky
WTHRESH
Rsvd
HTHRESH
Rsvd
PTHRESH
Write-back Threshold. This field controls the write-back
of processed transmit descriptors. This threshold refers to
the number of transmit descriptors in the GbE hardware
buffer which are ready to be written back to host memory.
In the absence of external events (explicit flushes), the
write-back will occur only after more than WTHRESH
descriptors are available for write-back.
Since write-back notification of transmit descriptor
completion is optional (under the control of the RS bit in
the descriptor), not all processed descriptors are counted
with respect to WTHRESH (any single transmit descriptor
with RS=0 is consumed with no writeback notification
performed). When WTHRESH is non-zero, processing a
descriptor with RS=1 initiates accumulation of pending
writebacks; accumulated writebacks will include even
those descriptors with RS=0, in order to optimize
writeback bursts.
Note: When WTHRESH value is set to 0, transmit
descriptor writeback notification will be similar to
the 82452 behavior. In accordance with
WTHRESH=0, the writeback notification for a
descriptor with RS=1 will occur as soon as the
descriptor is processed. In addition, processed
transmit descriptors are not written-back in
entirety; only the descriptor status field is written
back/ updated. This 82542-compatible mode is
the default HW behavior.
Reserved
Host Threshold. This field is used to control the fetching
of descriptors from host memory. This threshold refers to
the number of valid, unprocessed receive descriptors that
must exist in host memory before they will be fetched.
Reserved
Prefetch Threshold. This field is used to control when a
prefetch of descriptors will be considered. This threshold
refers to the number of valid, unprocessed transmit
descriptors the chip has in its GbE hardware buffer. If this
number drops below PTHRESH, the algorithm will consider
pre-fetching descriptors from host memory. This fetch will
not happen however unless there are at least HTHRESH
valid descriptors in host memory to fetch.
Bit Reset
Value
0h
0h
0h
0h
0h
Bit Access
RW
RV
RW
RV
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1501