EP80579 Datasheet, PDF (714/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
— Detects if data on first read is FFh (indicates unprogrammed Firmware Hub).
18.2
Note:
Warning:
Note:
TCO I/O-Mapped Configuration Register Details
The TCO logic is accessed via registers mapped to the PCI configuration space (Device
31, Function 0) and the system I/O space. For TCO PCI Configuration registers, see
Section 19.0, “LPC Interface: Bus 0, Device 31, Function 0”.
For more information on the format of the register description tables that follow in this
chapter, see Section 7.1.1, “Register Description Tables” on page 183).
Address locations that are not listed are considered reserved register locations. Reads
to reserved registers may return non-zero values and are read only. Writes to reserved
locations may cause system failure and unpredictable results.
Reserved bits are Read Only.
Table 18-1. Bus 0, Device 31, Function 0: Summary of TCO Configuration Registers
Mapped Through TCOBASE I/O BAR“
Offset Start Offset End
Register ID - Description
00h
02h
03h
04h
06h
08h
0Ah
0Ch at 01h
0Eh
10h
12h
01h
02h
03h
04h
07h
09h
0Bh
0Ch at 01h
0Eh
10h
13h
“Offset 00h: TRLD - TCO Timer Reload and Current Value Register” on page 715
“Offset 02h: TDI - TCO Data In Register” on page 715
“Offset 03h: TDO - TCO Data Out Register” on page 716
“Offset 04h: TSTS1 - TCO 1 Status Register” on page 716
“Offset 06h: TSTS2 - TCO 2 STS Register” on page 718
“Offset 08h: TCTL1 - TCO 1 Control Register” on page 720
“Offset 0Ah: TCTL2 - TCO 2 Control Register” on page 721
“Offset 0Ch: TMSG[1-2] - TCO MESSAGE Register” on page 721
“Offset 0Eh: TWDS - TCO Watchdog Status Register” on page 722
“Offset 10h: LE - Legacy Elimination Register” on page 722
“Offset 12h: TTMR - TCO Timer Initial Value Register” on page 723
Default
Value
0000h
00h
00h
0000h
0000h
0000h
0008h
00h
00h
03h
0004h
Intel^® EP80579 Integrated Processor Product Line Datasheet
714
August 2009
Order Number: 320066-003US