EP80579 Datasheet, PDF (157/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 5-28. Summary of CAN Error Conditions
Event
Type
Fatality^a
Reports via
Notes
CRC Check Error Uncorrectable
Acknowledge Error Uncorrectable
Form Error
Uncorrectable
Bit Error
Uncorrectable
Stuff Error
Uncorrectable
Fatal
Fatal
Fatal
Fatal
Fatal
CAN SRAM Parity
Error
Uncorrectable
Fatal
CAN System
Interrupt
CAN System
Interrupt
CAN System
Interrupt
CAN System
Interrupt
CAN System
Interrupt
CAN Parity
Interrupt
Mismatch between received and
computed CRC.
Improperly formatted ACK slot.
Improperly formatted fixed-form field.
Mismatch between monitored and sent
bit value.
Improperly formatted message from
Start of Frame to CRC delimiter.
Parity error in interface SRAM.
Clearing the parity error requires a
reset of the CAN interface. Please see
section on CAN interrupts in Section
39.2, “Feature List” on page 1569 for
more details.
a. “Fatal” events result in data loss or data corruption that the unit cannot repair, “Non-Fatal” events do not.
Table 5-29 summarizes the capabilities of the CAN error handling for each of the
features that the unit is expected to provide.
Table 5-29. Summary of CAN Error Reporting Capabilities
Feature
Implementation
Enabling and
Masking Error
Reporting
The CAN interrupt enable register supports error enabling and masking.
The SMIA and SMME registers from the signal target capability in the PCI configuration
header for the CAN units also supports error enabling and masking. Using these registers
to mask the CAN System Interrupt masks both error and functional events since the CAN
units use this interrupt to signal both error and functional conditions.
Logging Details
The SINT register from the signal target capability in the PCI configuration header for a
CAN unit provides read-only access to the state of the interrupt signals from a CAN unit.
CAN does not log additional details on errors.
Reporting Multiple Individual status bits in CAN interrupt status register are set as conditions occur. The unit
Errors
can indicate at most one outstanding error of each type at any time.
Data Poisoning
CAN does not require support for data poisoning. Errors during transactions cause the
transaction to abort and an error event to be signaled.
See Section 39.6, “Register Summary” and Section 39.5.2, “Error Handling” for
additional details.
5.6.3
SSP Interface
The SSP unit signals error conditions through a single interrupt signal. The SSP block
shares this interrupt between functional duties (e.g., transmit FIFO service request)
and error reporting duties. Software is expected to use status registers in the SSP to
determine the cause of a signal.
Table 5-30 summarizes the error condition that the SSP captures.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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