EP80579 Datasheet, PDF (913/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
24.3.1.5 Offset 05h: HD0: Data 0 Register
Table 24-23. Offset 05h: HD0: Data 0 Register
Description:
View: PCI
BAR: SM_BASE (IO)
Bus:Device:Function: 0:31:3
Offset Start: 05h
Offset End: 05h
Size: 8 bit
Default: 00h
Power Well: Resume
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
This field contains the eight bit data sent in the DATA0
field of the SMB protocol. For block write commands,
this register reflects the number of bytes to transfer.
DATA0_COUNT This register should be programmed to a value between
1 and 32 for block counts. A count of 0 or a count above
32 will result in unpredictable behavior. The host
controller does not check or log illegal block counts.
Bit Reset
Value
00h
Bit Access
RW
24.3.1.6 Offset 06h: HD1: Data 1 Register
Table 24-24. Offset 06h: HD1: Data 1 Register
Description:
View: PCI
BAR: SM_BASE (IO)
Bus:Device:Function: 0:31:3
Offset Start: 06h
Offset End: 06h
Size: 8 bit
Default: 00h
Power Well: Resume
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
DATA1
This eight bit register is transmitted in the DATA1 field
of the SMB protocol during the execution of any
command.
Bit Reset
Value
00h
Bit Access
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
913