EP80579 Datasheet, PDF (926/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
To support these devices, the CMI implements an I²C Read command with the following
format:
Note:
Note:
24.4.2.8
Bit
Description
1
2–8
9
10
11 – 18
19
20
21 – 27
28
29
30 – 37
38
39 – 46
47
...
...
...
...
Start
Slave Address - 7 bits
Write
Acknowledge from slave
Send DATA1 register
Acknowledge from slave
Repeated Start
Slave Address - 7 bits
Read
Acknowledge from slave
Data Byte 1 from slave - 8 bits
Acknowledge
Data Byte 2 from slave - 8 bits
Acknowledge
Data Bytes from slave/Acknowledge
Data Byte N from slave - 8 bits
NOT Acknowledge
Stop
The CMI continues reading data from the peripheral until the NAK is received.
This new command is supported independent of the setting of the I2C_EN bit.
The value written into bit 0 of the Transmit Slave Address register (SMBus Offset 04h)
must be 0.
Block Write-Block Read Process Call
The block write-block read process call is a two-part message. The call begins with a
slave address and a write condition. After the command code the host issues a write
byte count (M) that describes how many more bytes will be written in the first part of
the message. If a master has six bytes to send, the byte count field will have the value
6 (0000 0110b), followed by the six bytes of data. The write byte count (M) cannot be
zero.
The second part of the message is a block of read data beginning with a repeated start
condition followed by the slave address and a read bit. The next byte is the read byte
count (N), which may differ from the write byte count (M). The read byte count (N)
cannot be zero.
The combined data payload must not exceed 32 bytes. The byte length restrictions of
this process call are summarized as follows:
• M ≥ 1 byte
• N ≥ 1 byte
• M + N ≤ 32 bytes
The read byte count does not include the PEC byte. The PEC is computed on the total
message beginning with the first slave address and using the normal PEC
computational rules. It is highly recommended that a PEC byte be used with the block
write-block read process call. Software must do a read to the command register (offset
2h) to reset the 32 byte buffer pointer prior to reading the block data register.
Intel^® EP80579 Integrated Processor Product Line Datasheet
926
August 2009
Order Number: 320066-003US