EP80579 Datasheet, PDF (579/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.64 Offset 118h: AERCACR - Advanced Error Capabilities and
Control Register
This register identifies the capability structure and points to the next structure. The
first error pointer rearms after the unmasked errors have been cleared. Software after
clearing the errors must read the register again to ensure that it is indeed cleared. If it
finds that another error occurred, it can not rely on the pointer or header, unless it
detects that the error pointer changed from the last time it was read for the previous
error. Bits in this register also declare the ECRC capability of this device. These bits are
sticky through reset.
Table 16-203.Offset 118h: AERCACR - Advanced Error Capabilities and Control Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 118h
Offset End: 11Bh
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 118h
Offset End: 11Bh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 09
08
07
06
05
04 : 00
Bit Acronym
Bit Description
Sticky
Reserved Reserved
ECE
ECRC Check Enable
Note: ECRC is not supported for the EP80579.
Y
EC
ECRC Check Capable
Note: ECRC is not supported for the EP80579.
EGE
ECRC Generation Enable
Note: ECRC is not supported for the EP80579.
Y
EGC
ECRC Generation Capable
Note: ECRC is not supported for the EP80579.
First error pointer identifies the bit position of the first
error reported in the Uncorrectable Error Status register.
However, if a subsequent Uncorrectable Error occurs with a
higher severity, this field is over-written with the bit
position of the subsequent error status bit. Also, if multiple
FEP
errors of equal severity are logged simultaneously, this
Y
field identifies the bit position of the most significant
(leftmost) bit that has been set in the Uncorrectable Error
Status register. In the event of simultaneous errors, the
pointer indicates the least significant bit of the group. This
bit is sticky through system reset.
Bit Reset
Value
000000h
0b
0b
0b
0b
00000b
Bit Access
RO
RO
RO
RO
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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