EP80579 Datasheet, PDF (30/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
27.8.5 Processor Thermal Trip.......................................................................... 1089
27.8.6 SATA SCI ............................................................................................ 1090
27.8.7 PCI Express* PME Event Message ........................................................... 1090
27.9 Alternate (ALT) Access Mode ........................................................................... 1091
27.9.1 Write Only Registers with Read Paths in Alternate Access Mode .................. 1091
27.9.2 PIC Reserved Bits ................................................................................. 1093
27.9.3 Read-Only Registers with Write Paths in ALT Access Mode.......................... 1094
27.10 System Power Supplies, Planes, and Signals...................................................... 1094
27.10.1 Power Plane Control with SLP_S3#, SLP_S4# and SLP_S5# ....................... 1094
27.10.2 SLP_S4# and Suspend-To-RAM Sequencing ............................................. 1094
27.10.3 PWROK Signal ...................................................................................... 1095
27.10.4 CPUPWRGD Signal ................................................................................ 1095
27.10.5 Controlling Leakage and Power Consumption During Low-Power States........ 1095
27.10.6 VRMPWROK ......................................................................................... 1096
27.11 Legacy Power Management Theory of Operation ................................................ 1096
27.11.1 Overview............................................................................................. 1096
27.11.2 APM Power Management........................................................................ 1096
28.0 IA-32 Core Interface ............................................................................................ 1097
28.1 IA-32 Core Interface I/O-Mapped Register Details .............................................. 1097
28.1.1 Register Descriptions ............................................................................ 1098
28.1.1.1
28.1.1.2
28.1.1.3
28.1.1.4
28.1.1.5
Offset 61h: NMI_SC - NMI Status and Control Register....................... 1098
Offset 70h: NMI_EN - NMI Enable (and Real Time Clock Index)
Register ....................................................................................... 1099
Offset 92h: PORT92 - Fast A20 and Init Register ............................... 1100
Offset F0h: COPROC_ERR - Coprocessor Error Register ...................... 1100
Offset CF9h: RST_CNT - Reset Control Register ................................. 1101
28.2 IA-32 Core Interface Signals .......................................................................... 1102
28.2.1 A20M# (Mask A20) ............................................................................... 1102
28.2.2 INIT# (Initialization) ............................................................................. 1102
28.2.3 INTR# (Interrupt Signals)...................................................................... 1103
28.2.4 STPCLK# and CPUSLP# (Stop Clock Request and Processor Sleep Signals) ... 1103
28.2.5 Enhanced Intel SpeedStep Technology (EIST) Signals................................ 1103
28.2.6 DPSLP# (Deeper Sleep)......................................................................... 1103
29.0 Real Time Clock ................................................................................................... 1105
29.1 Overview ...................................................................................................... 1105
29.2 RTC I/O Registers .......................................................................................... 1105
29.3 Real Time Clock Indexed Register Details .......................................................... 1106
29.3.1 Real Time Clock Register Details ............................................................. 1107
29.3.1.1
29.3.1.2
29.3.1.3
29.3.1.4
Offset 0Ah: RTC_REGA - Register A (General Configuration) ............... 1107
Offset 0Bh: RTC_REGB - Register B (General Configuration) ............... 1109
Offset 0Ch: RTC_REGC - Register C (Flag Register)............................ 1110
Offset 0Dh: RTC_REGD - Register D (Flag Register) ........................... 1111
29.4 Update Cycles ............................................................................................... 1112
29.5 Interrupts ..................................................................................................... 1112
29.6 Lockable RAM Ranges..................................................................................... 1112
29.7 Century Rollover............................................................................................ 1112
29.8 Month and Year Alarms .................................................................................. 1113
30.0 Interrupts ............................................................................................................ 1115
30.1 Overview ...................................................................................................... 1115
30.2 8259 Interrupt Controllers (PIC) ...................................................................... 1117
30.2.1 Overview............................................................................................. 1117
30.2.2 I/O Registers ....................................................................................... 1118
30.2.2.1 ICW1[0-1] - Initialization Command Word 1 Register ......................... 1119
30.2.2.2 ICW2[0-1] - Initialization Command Word 2 Register ......................... 1120
Intel^® EP80579 Integrated Processor Product Line Datasheet
30
August 2009
Order Number: 320066-003US