EP80579 Datasheet, PDF (1682/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
However, there are some special things to note when using the Expansion Bus in HPI
mode of operation. These features are shown in the following tables. There are also
some restrictions on the timing parameters and these are outlined in Section 42.4.1.3,
“Expansion Bus Interface Configuration” on page 1676.
The Expansion-bus address-pins bits 0, 1, 2, 22, and 23 are multiplexed with special
function signal pins for HPI as shown in Table 42-3.
Table 42-3. Multiplexed Output Pins for HPI Operation
HPI Control Signal
EX_HBIL
EX_HCNTL [1:0]
EX_HCSEL [1:0]
Output Signal Pin
EX_ADDR [0]
EX_ADDR [2:1]
EX_ADDR [23:22]
The byte identification signal, EX_HBIL, is used to determine the byte transfer order.
(EX_HBIL is driven low for the first byte of the transfer and driven high for the second
byte.)
The byte order bit (BOB) in the HPIC register (contained in the DSP) — within the HPI
device — is used to determine the placement for the two bytes of the transfer. Please
consult the datasheet of the specific DSP being connected to determine the order of the
transferred bytes.
When operating in HPI mode, bits 13:10 in the Timing and Control (EXP_TIMING_CS)
Registers are ignored.
When operating in HPI-16, non-multiplexed mode, the Expansion bus address bus
provides direct accesses to the DSP memory space. The data associated with this
address will be read or written from the location specified by the value contained on the
Expansion Bus address bits.The signals EX_HCNTL [1:0] are multiplexed onto the
EX_ADDR [2:1] pins. When communicating to a multiplexed HPI interface, the
EX_HCNTL [1:0] signals are used to select one of four internal registers used for
interfacing to the DSP. The EX_HCNTL [1:0] mapping is described in the Table 42-4.
Table 42-4. HPI HCNTL Control Signal Decoding
hcntl[1:0]
00
01
10
11
Required Access
Read / write control register (HPIC)
Read / write data register (HPID)
HPI-8:
Post-increment HPIA on reads, pre-increment on writes.
HPI-16:
Post-increment HPIA on reads and writes
Read / write address register (HPIA)
Read / write data register (HPID)
42.4.1.7
Expansion Bus Outbound Timing Diagrams
The STATE signal that is shown in some of the following timing diagrams is the internal
state of the Expansion bus controller.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1682
August 2009
Order Number: 320066-003US