EP80579 Datasheet, PDF (63/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
16-178 Offset 5Ah: MSICAPA - MSI Capabilities Register ................................................ 553
16-179 Offset 5Ch: MSIAR - MSI Address for PCI Express Register .................................. 553
16-180 Offset 60h: MSIDR - MSI Data Register ............................................................. 554
16-181 Offset 64h: PEACAPID - PCI Express Features Capabilities ID Register ................... 555
16-182 Offset 65h: PEANPTR - PCI Express Next Capabilities Pointer Register ................... 556
16-183 Offset 66h: PEACAPA - PCI Express Features Capabilities Register ........................ 556
16-184 Offset 68h: PEADEVCAP - PCI Express Device Capabilities Register ....................... 557
16-185 Offset 6Ch: PEADEVCTL - PCI Express Device Control Register ............................. 558
16-186 Offset 6Eh: PEADEVSTS - PCI Express Device Status Register ............................... 560
16-187 Offset 70h: PEALNKCAP - PCI Express Link Capabilities Register ........................... 561
16-188 Offset 70h: PEA1LNKCAP - PCI Express Link Capabilities Register ......................... 561
16-189 Offset 74h: PEALNKCTL - PCI Express Link Control Register ................................. 562
16-190 Offset 76h: PEALNKSTS - PCI Express Link Status Register .................................. 564
16-191 Offset 78h: PEASLTCAP - PCI Express Slot Capabilities Register ............................ 565
16-192 Offset 78h: PEA1SLTCAP - PCI Express Slot Capabilities Register .......................... 566
16-193 Offset 7Ch: PEASLTCTL - PCI Express Slot Control Register .................................. 568
16-194 Offset 7Eh: PEASLTSTS - PCI Express Slot Status Register ................................... 569
16-195 Offset 80h: PEARPCTL - PCI Express Root Port Control Register ............................ 570
16-196 Offset 84h: PEARPSTS - PCI Express Root Port Status Register ............................. 571
16-197 Offset 100h: ENHCAPST - Enhanced Capability Structure Register ......................... 571
16-198 Offset 104h: UNCERRSTS - Uncorrectable Error Status Register ............................ 572
16-199 Offset 108h: UNCERRMSK - Uncorrectable Error Mask Register ............................. 574
16-200 Offset 10Ch: UNCERRSEV - Uncorrectable Error Severity Register .......................... 575
16-201 Offset 110h: CORERRSTS - Correctable Error Status Register ................................ 576
16-202 Offset 114h: CORERRMSK - Correctable Error Mask Register ................................ 578
16-203 Offset 118h: AERCACR - Advanced Error Capabilities and Control Register ............. 579
16-204 Offset 11Ch: HDRLOG0 - Header Log DW 0 (1st 32 bits) Register ......................... 580
16-205 Offset 120h: HDRLOG1 - Header Log DW 1 (2nd 32 bits) Register ........................ 580
16-206 Offset 124h: HDRLOG2 - Header Log DW 2 (3rd 32 bits) Register .......................... 581
16-207 Offset 128h: HDRLOG3 - Header Log DW 3 (4th 32 bits) Register ......................... 581
16-208 Offset 12Ch: RPERRCMD - Root (Port) Error Command Register ............................ 582
16-209 Offset 130h: RPERRMSTS - Root (Port) Error Message Status Register ................... 583
16-210 Offset 134h: ERRSID - Error Source ID Register ................................................. 585
16-211 Offset 140h: PEAUNITERR - PCI Express Unit Error Register ................................. 586
16-212 Offset 144h: PEAMASKERR - PCI Express Unit Mask Error Register ........................ 588
16-213 Offset 148h: PEAERRDOCMD - PCI Express Error Do Command Register ................ 589
16-214 Offset 14Ch: UNCEDMASK - Uncorrectable Error Detect Mask Register ................... 591
16-215 Offset 150h: COREDMASK - Correctable Error Detect Mask Register ...................... 592
16-216 Offset 158h: PEAUNITEDMASK - PCI Express Unit Error Detect Mask Register ......... 594
16-217 Offset 160h: PEAFERR - PCI Express First Error Register ....................................... 595
16-218 Offset 164h: PEANERR - PCI Express Next Error Register ..................................... 597
16-219 Offset 168h: PEAERRINJCTL - Error Injection Control Register .............................. 597
16-220 Bus 0, Device 0, Function 0: Summary of IMCH SMRBASE Registers ....................... 599
16-221 Offset 00h: NOTESPAD - Note (Sticky) Pad for BIOS Support Register ................... 601
16-222 Offset 02h: NOTEPAD - Note Pad for BIOS Support Register ................................. 601
16-223 Offset 40h: DCALCSR – DCAL Control and Status Register ................................... 602
16-224 DCALCSR.OPMODS in Receive Enable Mode ......................................................... 604
16-225 DCALCSR.OPMODS in ZQ Calibration Mode .......................................................... 604
16-226 Rules about issuing Self-Refresh and Refresh commands using DCALCSR.OPCODE .... 604
16-227 DCALCSR.OPMODS in DQS Cal Mode................................................................... 605
16-228 DCALCSR.OPMODS in Error Monitor/Read DDRIO FIFO Mode.................................. 605
16-229 Offset 44h: DCALADDR - DCAL Address Register .................................................. 606
16-230 Interpretation of DCALADDR based on DCALCSR.OPCODE...................................... 606
16-231 Offset 48h: DCALDATA[0-71] - DRAM Calibration Data Register.............................. 607
16-232 DCALDATA Based on DCALCSR.OPCODE.............................................................. 608
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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