EP80579 Datasheet, PDF (249/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 7-65. Bus M, Device 7, Function 0: Summary of IEEE 1588 TSYNC CSRs (Sheet 2 of
2)
Offset Start Offset End
Register ID - Description
0000204h
00000208h
0000020Ch
0000207h
0000020Bh
0000020Fh
“Offset 0204h: User Defined EtherType Register” on page 1669
“Offset 0208h:User Defined Header Offset Register” on page 1670
“Offset 020Ch:User Defined Header Register” on page 1670
Default
Value
00000000h
00000000h
00000000h
7.4.7
Local Expansion Bus Interface: Bus M, Device 8, Function 0:
The Local Expansion Bus interface includes the registers listed in Table 7-66 and
Table 7-67. These registers materialize in PCI configuration and memory (via PCI BAR)
spaces. See Section 35.12, “Expansion Bus Configuration Space: Bus M, Device 8,
Function 0”, and Table 42.5, “Register Summary” on page 1696 for detailed discussion
of these registers along with alternative materializations.
Table 7-66. Bus M, Device 8, Function 0: Summary of Local Expansion Bus PCI
Configuration Registers (Sheet 1 of 2)
Offset Start Offset End
Register ID - Description
00h
02h
04h
06h
08h
09h
0Eh
10h
14h
2Ch
2Eh
34h
3Ch
3Dh
40h
DCh
DDh
DEh
E0h
E4h
E5h
E6h
01h
03h
05h
07h
08h
0Bh
0Eh
13h
17h
2Dh
2Fh
34h
3Ch
3Dh
43h
DCh
DDh
DFh
E1h
E4h
E5h
E6h
“Offset 00h: VID: Vendor Identification Register” on page 1320
“Offset 02h: DID: Device Identification Register” on page 1320
“Offset 04h: PCICMD: Device Command Register” on page 1321
“Offset 06h: PCISTS: PCI Device Status Register” on page 1321
“Offset 08h: RID: Revision ID Register” on page 1322
“Offset 09h: CC: Class Code Register” on page 1323
“Offset 0Eh: HDR: Header Type Register” on page 1323
“Offset 10h: CSRBAR: Control and Status Registers Base Address Register” on
page 1323
“Offset 14h: MMBAR: Expansion Bus Base Address Register” on page 1324
“Offset 2Ch: SVID: Subsystem Vendor ID Register” on page 1325
“Offset 2Eh: SID: Subsystem ID Register” on page 1325
“Offset 34h: CP: Capabilities Pointer Register” on page 1326
“Offset 3Ch: IRQL: Interrupt Line Register” on page 1326
“Offset 3Dh: IRQP: Interrupt Pin Register” on page 1326
“Offset 40h: LEBCTL: LEB Control Register” on page 1327
“Offset DCh: PCID: Power Management Capability ID Register” on page 1327
“Offset DDh: PCP: Power Management Next Capability Pointer Register” on
page 1328
“Offset DEh: PMCAP: Power Management Capability Register” on page 1328
“Offset E0h: PMCS: Power Management Control and Status Register” on
page 1329
“Offset E4h: SCID: Signal Target Capability ID Register” on page 1329
“Offset E5h: SCP: Signal Target Next Capability Pointer Register” on page 1330
“Offset E6h: SBC: Signal Target Byte Count Register” on page 1330
Default
Value
8086h
503Dh
0000h
0010h
Variable
068000h
00h
00000000h
00000000h
0000h
0000h
DCh
00h
01h
00h
01h
E4h
0023h
0000h
09h
F0h
09h
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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