EP80579 Datasheet, PDF (1174/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
before the unit is enabled. When the unit is disabled, the transmitter/receiver finishes
the current byte being transmitted/received if it is in the middle of transmitting/
receiving a byte and stops transmitting/receiving more data.
An SIU_RESET# to the SIU forces the internal register and output signals on the serial
port to the values listed below.
Table 33-6. UART Register/Signal Reset States
Register/Signal
Interrupt Enable Register
Interrupt ID Register
Line Control Register
Line Status Register
Modem Control Register
Modem Status Register
Infrared Selection Register
Txd
Int
rts_n
dtr_n
Reset Control
RESET
RESET
RESET
RESET
RESET
RESET/Modem signal,
read MSR for bits 3-0.
RESET
RESET
RESET/ clear LINE
STATUS REG
RESET
RESET
Reset State
All bits are low.
Bit 0 is forced high. Bits 1-3 and 6-7 are forced
low. Bits 4-5 are permanently low.
All bits are forced low.
Bits 0-4,7 are forced low. Bits 5 and 6 are forced
high.
Bits 0,1,2,3,4 are forced low. Bits 5,6,7 are
permanently low.
Low
All bits are permanently low.
High
Low
High
High
33.5.2.1
Note:
Programmable Baud Rate Generator
The UART contains a programmable Baud Rate Generator that is capable of taking the
UART_CLK input and dividing it by any divisor from 1 to (2 ¹⁶ -1). The output frequency
of the Baud Rate Generator is 16 times the baud rate. Two 8-bit latches store the
divisor in a 16-bit binary format. These Divisor Latches must be loaded during
initialization to ensure proper operation of the Baud Rate Generator. If both Divisor
Latches are loaded with 0, the 16X output clock is stopped. Upon loading either of the
Divisor latches, a 16-bit baud counter is immediately loaded. This prevents long counts
on initial load. Access to the Divisor latch can be done with a word write.
The UART_CLK is the SIW_CLK input divided by the prescalar set by the SIW
Configuration Register (Offset 29h).
The baud rate of the data shifted in/out of the UART is given by:
Baud Rate = UART_CLK(MHz)/[16X Divisor]
For example, if UART_CLK is 14.7456MHz and the divisor is 96, the baud rate is 9600.
A Divisor value of 0 in the Divisor Latch Register is not allowed. The reset value of the
divisor is 02.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1174
August 2009
Order Number: 320066-003US