EP80579 Datasheet, PDF (1186/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 33-20. Offset 05h: LSR - Line Status Register (Sheet 1 of 3)
Description:
View: IA F
Base Address: Base (IO)
Offset Start: 05h
Offset End: 05h
Size: 8 bit
Default: 60h
Power Well: Core
Bit Range
07
06
05
Bit Acronym
Bit Description
Sticky
FIFOE
TEMT
TRDQ
FIFO Error Status: This bit is reset only when all the
error bytes have been read from the FIFO. A processor
read to the Line Status register does not reset this bit.
Non-FIFO mode:
0 = Bit is always “0” indicating no FIFO.
FIFO mode:
0 = All error bytes have been read from the FIFO
1 = At least one character in the receiver FIFO contains
a parity error, framing error, or break indication.
When DMA requests are enabled (IER bit7 is set to 1)
and FIFOE is set to 1, no receive DMA request is
generated even though the receive FIFO reaches the
trigger level and the error interrupt is generated.
When DMA requests are not enabled (IER bit7 is set to
0), FIFOE set to 1 does not generate interrupt.
Transmitter Empty:
Non-FIFO mode:
0 = Either the Transmit Holding register or the
Tansmitter Shift register contain a data character.
1 = The Transmit Holding register and the Transmitter
Shift register are both empty.
FIFO mode:
0 = Either the transmitter FIFO or the Transmit Shift
register contain a data character.
1 = The transmitter FIFO and the Transmit Shift
register are both empty.
Transmit Data Request: TDRQ indicates that the
UART is ready to accept a new character for
transmission. In addition, this bit causes the UART to
issue an interrupt to the processor when the transmit
data request interrupt enable is set high.
Non-FIFO mode:
0 = No character transferred from the Transmit Holding
register into the Transmit Shift register.
1 = A character has transferred from the Transmit
Holding register into the Transmit Shift register.
Note: Bit is reset to logic 0 with the loading of the
Transmit Holding register by the processor.
FIFO mode:
0 = When at least one byte is written to the transmit
FIFO. When more than 16 characters are loaded
into the FIFO, the excess characters are lost.
1 = Transmit FIFO is empty or the RESETTF bit in FCR,
has been set to 1.
Bit Reset
Value
0b
1b
1b
Bit Access
RO
RO
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
1186
August 2009
Order Number: 320066-003US