EP80579 Datasheet, PDF (693/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
17.1.1.5 Offset 000Eh: PVS - Port Virtual Channel Status Register
Table 17-7. Offset 000Eh: PVS -Port Virtual Channel Status Register
Description:
View: PCI
BAR: RCBA
Bus:Device:Function: 0:31:0
Offset Start: 000Eh
Offset End: 000Fh
Size: 16 bit
Default: 0h
Power Well: Core
Bit Range
15 :01
00
Bit Acronym
Bit Description
Sticky
Reserved
VAS
Reserved
VC Arbitration Table Status: Indicates the coherency
status of the VC Arbitration table when it is being updated.
This field is hardwired to 0 in the root complex since there
is no VC arbitration table.
Bit Reset
Value
0000h
0h
Bit Access
RO
17.1.1.6 Offset 0010h: V0CAP - Virtual Channel 0 Resource Capability Register
Table 17-8. Offset 0010h: V0CAP - Virtual Channel 0 Resource Capability Register
Description:
View: PCI
BAR: RCBA
Bus:Device:Function: 0:31:0
Offset Start: 0010h
Offset End: 0013h
Size: 32 bit
Default: 00000001h
Power Well: Core
Bit Range
31 :24
23
22 :16
15
14
13 :08
07 :00
Bit Acronym
Bit Description
Sticky
AT
Reserved
MTS
RTS
APS
Reserved
PAC
Port Arbitration Table Offset: This VC implements no
port arbitration table since the arbitration is fixed.
Reserved
Maximum Time Slots: This VC implements fixed
arbitration, and therefore this field is not used.
Reject Snoop Transactions: This VC must be able to
take snoopable transactions.
Advanced Packet Switching: This VC is capable of all
transactions, not just advanced packet switching
transactions.
Reserved
Port Arbitration Capability: Indicates that this VC uses
fixed port arbitration.
Bit Reset
Value
00h
0h
00h
0h
0h
0h
01h
Bit Access
RO
RO
RO
RO
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
693