EP80579 Datasheet, PDF (1374/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Figure 37-25.TCP/IP Data Transmit Descriptor Command Field (TDESC.DCMD)
Rsvd: Reserved (must be set to 0)
RS: Report Status
TSE: TCP Segmentation Enable
IFCS Insert FCS
EOP End of Packet
TSE indicates that this descriptor is part of the current TCP Segmentation context. If
this bit is not set, the descriptor is part of the “normal” context.
A packet is sent from one or more data buffers in host memory. The EOP bit indicates
that the buffer associated with this descriptor contains the last data for the packet or
given TCP segmentation context. In the case of a TCP Segmentation context, the
DTALEN length of this descriptor should match the amount remaining of the original
PAYLEN. If it does not, the TCP Segmentation context will be terminated but the end of
packet processing may be incorrectly performed. These abnormal termination events
will be counted in the TSCTFC statistics register detailed in Section 37.6.6.53, “TSCTFC
– TCP Segmentation Context Transmit Fail Count Register”.
IFCS controls insertion of the Ethernet CRC.
RS tells the hardware to report the status information for this descriptor as soon as the
corresponding data buffer has been fetched and stored in the EP80579’s GbE internal
packet buffer. Refer to Figure 37-26 for the layout of the status field.
The DEXT bit identifies this descriptor as one of the extended descriptor types and
must be set to 1.
VLE indicates that the packet is a VLAN packet (i.e. that the hardware should add the
VLAN Ethertype and an 802.1q VLAN tag to the packet).
Note:
If the VLE bit to enable VLAN tag insertion, the CTRL.VME bit should also be set. If the
CTRL. VME bit is not set, the device will not insert VLAN tags on outgoing packets.
Table 37-3. VLAN Tag Insertion Decision Table
VLE
0
1
Action
Send generic Ethernet packet. IFCS controls insertion of FCS in normal Ethernet
packets.
Send 802.1Q packet; the Ethernet Type field comes from the VET register and the
VLAN data comes from the special field of the TX descriptor; hardware always
appends the FCS/CRC.
Note:
The VLE, IFCS, and VLAN fields are only are only valid in certain descriptors. If TSE is
enabled, the VLE, IFCS, and VLAN fields are only valid in the first data descriptor of the
TCP segmentation context. If TSE is not enabled, then these fields are only valid in the
last descriptor of the given packet (qualified by the EOP bit).
IDE activates the transmit interrupt delay timer. Hardware loads a countdown register
when it writes back a transmit descriptor that has RS and IDE set. The value loaded
comes from Transmit Interrupt Delay Value Register (TIDV.IDV). When the count
reaches 0, a transmit interrupt occurs. Hardware always loads the transmit interrupt
counter whenever it processes a descriptor with IDE set even if it is already counting
down due to a previous descriptor. If hardware encounters a descriptor that has RS set,
but not IDE, it generates an interrupt immediately after writing back the descriptor and
the interrupt delay timer is cleared.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1374
August 2009
Order Number: 320066-003US