EP80579 Datasheet, PDF (850/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.2.2
23.2.2.1
23.2.2.2
23.2.2.3
23.2.3
23.2.3.1
Secondary Devices
Offset 08h: SCMD – Secondary Command Register
Same as that of primary device. See the description of “Offset 00h: PCMD – Primary
Command Register” on page 848.
Offset 0Ah: SSTS – Secondary Status Register
Same as that of primary device. See the description of “Offset 02h: PSTS – Primary
Status Register” on page 849.
Offset 0Ch: SDTP – Secondary Descriptor Table Pointer Register
Same as that of primary device. See the description of “Offset 04h: PDTP – Primary
Descriptor Table Pointer Register” on page 849.
AHCI Index and Data Registers
Offset 10h: INDEX – AHCI Index Register
Table 23-47. Offset 10h: INDEX – AHCI Index Register
Description:
View: PCI
BAR: LBAR (IO)
Bus:Device:Function: 0:31:2
Offset Start: 10h
Offset End: 13h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 10
09 : 02
01 : 00
Bit Acronym
Bit Description
Sticky
Reserved
INDEX
Reserved
Reserved
Index (INDEX): This Index register is used to select the
Dword offset of the Memory Mapped AHCI register to be
accessed. A Dword, Word or Byte access is specified by
the active byte enables of the I/O access to the Data
register.
Reserved
Bit Reset
Value
0h
0h
0h
Bit Access
RO
RW
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
850
August 2009
Order Number: 320066-003US