EP80579 Datasheet, PDF (1248/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
35.6.1.12 Offset 2Ch: SVID – Subsystem Vendor ID Register
This register is a write-once register. Once any byte in the register has been written,
the register locks against further writes until reset.
Table 35-17. Offset 2Ch: SVID: Subsystem Vendor ID Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: M:0:0
Offset Start: 2Ch
Offset End: 2Dh
View: PCI 2
BAR: Configuration
Bus:Device:Function: M:1:0
Offset Start: 2Ch
Offset End: 2Dh
View: PCI 3
BAR: Configuration
Bus:Device:Function: M:2:0
Offset Start: 2Ch
Offset End: 2Dh
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 00
Bit Acronym
Bit Description
Sticky
SVID
Subsystem Vendor ID: This field must be programmed
during BIOS initialization.
Bit Reset
Value
0h
Bit Access
RWO
35.6.1.13 Offset 2Eh: SID – Subsystem ID Register
This register is a write-once register. Once any byte in the register has been written,
the register locks against further writes until reset.
Table 35-18. Offset 2Eh: SID: Subsystem ID Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: M:0:0
Offset Start: 2Eh
Offset End: 2Fh
View: PCI 2
BAR: Configuration
Bus:Device:Function: M:1:0
Offset Start: 2Eh
Offset End: 2Fh
View: PCI 3
BAR: Configuration
Bus:Device:Function: M:2:0
Offset Start: 2Eh
Offset End: 2Fh
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
15 : 00
SID
Subsystem ID: This field must be programmed during
BIOS initialization.
Sticky
Bit Reset
Value
Bit Access
0h
RWO
35.6.1.14 Offset 34h: CP – Capabilities Pointer Register
The CP provides the offset to the location in configuration space where the first set of
capabilities registers is located.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1248
August 2009
Order Number: 320066-003US