EP80579 Datasheet, PDF (293/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
11.3.1
Rules for Populating DIMM Slots
1. In all configurations, the speed and timing will be the lowest among the 2 DIMMs,
as determined by the SPD registers on the DIMMs
2. Dual DIMM mode supports a subset of the DDR2 data speeds as shown in
Table 11-5.
3. Table 11-6 shows the supported DIMM population of the 2 ranks. All of
configurations not shown in Table 11-6 are not supported.The rank configurations
supported are one or two ranks on a single DIMM or one rank on each of the 2
DIMMs. Two ranks in each of the 2 DIMMs (i.e., 4 ranks) is not supported.
Table 11-6. Supported DIMM Populations
DIMM 1
DIMM 0
Rank 0
Rank 1
Rank 0
1 - Single Rank
Empty
Empty
DRB0
CS0
ODT0
1 - Dual Rank
Empty
Empty
DRB0
CS0
ODT0
2 - Single Rank
DRB2
CS1
ODT1
Empty
DRB0
CS0
ODT0
TABLE KEY:
ODT0/ODT1: ODT pins. Please refer to Section 11.4.2 for more information.
CS0/CS1: Chip Selects
DRB: Dram Row Boundary Register
Rank 1
Empty
DRB2
CS1
ODT1
Empty
4. Table 11-7 shows the supported rank configurations when using 2 ranks for the
single and dual DIMM.
.
Table 11-7. Supported Rank Configurations in Single and Dual DIMM mode
Single DIMM
(DDR2)
(64 bits - rank 0 & rank 1)
(32 bits - rank 0 only)
Dual DIMM
(DDR2, 64 bit only)
Rank 0
128 MB
(32 bit only)
256 MB
512 MB
1 GB
2 GB
Rank 1
NA
256 MB
512 MB
1 GB
2 GB
Rank 0, DIMM 0
NA
256 MB
512 MB
1 GB
2 GB
Rank 0, DIMM 1
NA
256 MB, 512 MB, 1 GB,
2 GB
256 MB, 512 MB, 1 GB,
2 GB
256 MB, 512 MB, 1 GB,
2 GB
256 MB, 512 MB, 1 GB,
2 GB
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
293