EP80579 Datasheet, PDF (642/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-288.Offset 264h: DDRIOMC1 - DDRIO Mode Register Control Register 1 (Sheet 1
of 2)
Description: DDRIOMC1: DDRIO Mode Control Register 1
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: 264h
Offset End: 267h
Size: 32 bit
Default: 52520000h
Power Well: Core
Bit Range
Bit Acronym
Bit Description
Sticky
CASLEW: The digital slew override 8-bit control allow for
balancing of pull-up and pull-down slew rates T for CA/CLK
buffers. The format of these controls and recommended
reset value is given below:
Bit Reset
Value
Bit Access
31 24
CASLEW
Bits
Function
DDR2Selection.
7
DDR2 = 0
6:5
Fast Corner falling
slew rate trim
4:2
Slow Corner falling
slew rate trim
1:0
Fast corner rising
slew rate trim
Y
01010010b
RW
23 16
DQSLEW: The digital slew override 8-bit control allow for
balancing of pull-up and pull-down slew rates T for CA/CLK
buffers. The format of these controls and recommended
reset value is given below:
DQSLEW
Bits
Function
DDR2 Selection.
7
DDR2 = 0
6:5
Fast Corner falling
slew rate trim
4:2
Slow Corner falling
slew rate trim
1:0
Fast corner rising
slew rate trim
Y
01010010b
RW
15 7
Reserved Reserved
N
000000000b
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
642
August 2009
Order Number: 320066-003US