EP80579 Datasheet, PDF (662/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-306.Offset 24h: NDUAR0 - Channel 0 Next Descriptor Upper Address Register
Description:
View: PCI
BAR: EDMALBAR
Bus:Device:Function: 0:1:0
Offset Start: 24h
Offset End: 27h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 00
Bit Acronym
Bit Description
Sticky
NDUADD
Next Descriptor Upper Address: The upper 32-bit
address of the next descriptor chain in memory to be
read by the channel. This field can only be written when
the Start bit in the CCR and the Channel Active bit in the
CSR are clear.
Bit Reset
Value
0000000h
Bit Access
RWL
16.6.1.11 Offset 28h: TCR0 - Channel 0 Transfer Count Register
The Transfer Count Register (TCR) contains the number of bytes it transfers. This
register is loaded when the transfer count field of the chain descriptor is read from
memory. The maximum allowed value for the TCR is 16 Mbytes. Values greater than 16
Mbytes are truncated to 16 Mbytes and no error is reported. A value of zero is valid and
results in no data being transferred and no cycles are generated on the source or
destination buses and an interrupt is generated if enabled. During transfers, this
register contains the remaining byte bytes to be written to the destination.
Table 16-307.Offset 28h: TCR0 - Channel 0 Transfer Count Register
Description:
View: PCI
BAR: EDMALBAR
Bus:Device:Function: 0:1:0
Offset Start: 28h
Offset End: 2Bh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 24
23 : 00
Bit Acronym
Bit Description
Sticky
Reserved
TCR0
Reserved
Transfer Count: Set by the IMCH when the transfer
count field of the chain descriptor is read from memory.
It reflects the number of bytes for a DMA transfer. A
value of 0 results in no data being transferred. The
maximum value that can be programmed to this
register is 16 Mbytes. Larger values written in the
transfer count field of the chain descriptor are
truncated, and no error is reported. Refer to
DCR0[18:17] for additional programming requirements
when in Constant Address Mode.
Bit Reset
Value
0000000h
000000h
Bit Access
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
662
August 2009
Order Number: 320066-003US