EP80579 Datasheet, PDF (1175/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
33.5.3
UART Register Details
There are 12 registers in the UART. These registers share eight address locations in the
I/O address space. Table 33-10 shows the registers and their addresses as offsets of a
base address. The state of the Divisor Latch Bit (DLAB), which is the MOST significant
bit of the Serial Line Control Register, affects the selection of certain of the UART
registers. The DLAB bit must be set high by the system software to access the Baud
Rate Generator Divisor Latches.
Table 33-7. Summary of UART Registers in I/O Space (DLAB=0)
Offset Start Offset End
Register ID - Description
00h
00h
“Offset 00h: RBR - Receive Buffer Register” on page 1176
00h
00h
“Offset 00h: THR - Transmit Holding Register” on page 1177
01h
01h
“Offset 01h: IER - Interrupt Enable Register” on page 1177
Default
Value
00h
00h
00h
Table 33-8. Summary of UART Registers in I/O Space (DLAB=1)
Offset Start Offset End
Register ID - Description
Default
Value
00h
00h
“Offset 00h: DLL - Programmable Baud Rate Generator Divisor Latch Register Low”
on page 1190
02h
01h
01h
“Offset 01h: DLH - Programmable Baud Rate Generator Divisor Latch Register
High” on page 1190
00h
Table 33-9. Summary of UART Timer registers in I/O space
Offset Start Offset End
Register ID - Description
02h
02h
“Offset 02h: IIR - Interrupt Identification Register” on page 1179
02h
02h
“Offset 02h: FCR - FIFO Control Register” on page 1180
03h
03h
“Offset 03h: LCR - Line Control Register” on page 1182
04h
04h
“Offset 04h: MCR - Modem Control Register” on page 1184
05h
05h
“Offset 05h: LSR - Line Status Register” on page 1186
06h
06h
“Offset 06h: MSR - Modem Status Register” on page 1189
07h
07h
“Offset 07h: SCR - Scratchpad Register” on page 1190
Default
Value
01h
00h
00h
00h
60h
00h
00h
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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