EP80579 Datasheet, PDF (1098/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
28.1.1
28.1.1.1
Register Descriptions
For more information on the format of the register description tables that follow in this
chapter, see Section 7.1.1, “Register Description Tables” on page 183.
Offset 61h: NMI_SC - NMI Status and Control Register
Table 28-3. Offset 61h: NMI_STS_CNT - NMI Status and Control Register
Description:
View: IA F
Base Address: 0000h (IO)
Offset Start: 61h
Offset End: 61h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
SERR# NMI Source Status:
0 = Bit is cleared when bit 2 is set to 1.
1 = Bit is set by any of the sources of the internal SERR
on IICH; this includes SERR assertions forwarded
from the secondary PCI bus, error from a port,
07
SERR_N_NMI_S
TS
Do_SERR or standard error message from internal
Bus 0 functions that generate SERR#. Bit 2 must be
cleared in this register in order for this bit to be set.
This interrupt source is enabled by setting bit 2 to 0.
To reset the interrupt, set bit 2 to 1 and then set it to
0.
This bit is read-only. When writing to port 61h, this bit
must be 0.
IOCHK# NMI Source Status:
0 = Bit is cleared when bit 3 is set to 1.
1 = Bit is set if a legacy agent (via SERIRQ) asserts ISA
06
IOCHK_
NMI_STS
IOCHK# and bit 3 is cleared (IOCHK_NMI_EN). This
interrupt source is enabled by setting bit 3 to 0. To
reset the interrupt, set bit 3 to 1and then set bit 3 to
0.
When writing to port 61h, this bit must be a 0.
Timer Counter 2 OUT Status: This bit reflects the
05
TMR2_
OUT_STS
current state of the 8254 counter 2 output. Counter 2
must be programmed following any PCI reset for this bit to
have a determinate value. When writing to port 61h, this
bit must be a 0.
Refresh Cycle Toggle: This signal toggles from either 0
to 1 or 1 to 0 at a rate that is equivalent to when refresh
04
REF_
TOGGLE
cycles would occur. When writing to port 61h, this bit must
be a 0.
Assumed for compatibility, although no legacy refreshes
occur. Must toggle at legacy refresh rate (every 15 μs).
IOCHK# NMI Enable:
03
IOCHK_
NMI_EN
0 = ISA IOCHK# NMIs are enabled.
1 = ISA IOCHK# NMIs are disabled and cleared.
PCI SERR# Enable:
02
PCI_SERR_EN 0 = SERR# NMIs are enabled.
1 = The SERR# NMIs are disabled and cleared.
Speaker Data Enable:
01
SPKR_DAT_EN
0=
1=
The SPKR output is a 0.
The SPKR output is equivalent to the Counter 2 OUT
signal value.
Timer Counter 2 Enable:
00
TIM_CNT2_EN 0 = Counter 2 counting is disabled.
1 = Counting is enabled.
Bit Reset
Value
0b
0b
0b
0b
0b
0b
0b
0b
Bit Access
RO
RO
RO
RO
RW
RW
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1098
August 2009
Order Number: 320066-003US