EP80579 Datasheet, PDF (1620/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
41.2.1
41.3
Note:
Note:
• Supports 15 ns resolution on the 1066 MHz and 1200 MHz SKUs.
• Supports 20 ns resolution on the 600MHz SKUs.
• Provides a Pulse Per Second output.
Signal Descriptions
• Auxiliary Slave Mode Snapshot – An active high level on this input causes a
snapshot of system time to be captured in the ASMS register. Refer to “Auxiliary
Snapshots” on page 4765 for usage and restrictions.
• Auxiliary Master Mode Snapshot – An active high level on this input causes a
snapshot of system time to be captured in the AMMS register. Refer to “Auxiliary
Snapshots” on page 4765 for usage and restrictions.
• Test Mode Data – This signal will reflect bits of the internal System Timer
depending on the setting of internal control bits in the TS_Test register.
• Pulse Per Second Output - This signal is asserted high when a match occurs
between the Compare register and lower 32 bits of system time. Clearing of this
signal is under firmware control. The register and pin can be used to create a pulse
per second event.
• Snapshot Taken Outputs – These 2 signals will each pulse high for eight (8)
pclks whenever a timestamp has been taken on the selected channel. (either TX or
RX). The channel that is monitored is determined by the control bits in the TS_Test
Register.
Functional Block Diagram
A programming model is shown in Figure 41-1, showing registers and interconnections.
If the functional block is the Master, the XMIT snapshot holds the “SYNC” message time
and the RECV snapshot holds the DELAY” message time. If the unit is the Slave, the
XMIT snapshot holds the “DELAY” message time and the RECV snapshot holds the
“SYNC” message time.
“Take snapshot” = Synch, edge detect, and lock, until reset by writing a “1” to the
corresponding bit in the event register.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1620
August 2009
Order Number: 320066-003US