EP80579 Datasheet, PDF (441/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-49. Offset 88h: SDRC - DDR SDRAM Secondary Control Register (Sheet 3 of 3)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 88h
Offset End: 8Bh
Size: 32 bit
Default: 00000002h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
Size of command queue available to ASU
The Scheduler implements a shared Command Queue
which is nominally 64 entries deep. This queue is shared
between ASU and IA traffic. In order to reserve some
queue entries for IA commands only, software is able to set
an upper limit on the number of ASU commands that can
ASU_CMDQSIZ ^{occupy this queue. If the number of ASU commands}
E
exceeds this programmed value, subsequent AIOC
N
commands may be backed off by the memory controller,
until ASU commands drain to DDR, and the number in the
command queue, once again, falls below the programmed
value.
Bit Reset
Value
00000010b
Bit Access
RW
Recommended value is 0x30. Do not set this field to 0.
16.1.1.46 Offset 8Ch: CKDIS – CK/CK# Clock Disable Register
This register is used to enable or disable the CK/CK# pins to the DIMMS. This feature is
intended to reduce EMI and power consumption due to clocks toggling to DIMMs that
are not populated.
Table 16-50. Offset 8Ch: CKDIS - CK/CK# Clock Disable Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 8Ch
Offset End: 8Ch
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
7 :06
05 :00
Bit Acronym
Bit Description
Sticky
Reserved Reserved
N
CKDIS
CK/CK# Disable (Sticky)
Each bit corresponds to a pair of CK pins. Default is
enabled.
0 = Enable CK signals
1 = Disable CK signals. When disabled, the CK/CK# signals
are tristated.
Bit 5: Enable/Disable CK[5]/CK#[5]
Y
Bit 4: Enable/Disable CK[4]/CK#[4]
Bit 3: Enable/Disable CK[3]/CK#[3]
Bit 2: Enable/Disable CK[2]/CK#[2]
Bit 1: Enable/Disable CK[1]/CK#[1]
Bit 0: Enable/Disable CK[0]/CK#[0]
Bit Reset
Value
00b
000000b
Bit Access
RO
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
441