EP80579 Datasheet, PDF (733/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
19.0
19.1
19.2
Note:
LPC Interface: Bus 0, Device 31, Function 0
Overview
The LPC bridge function IICH resides in PCI Device 31, Function 0. This contains many
other functional units, such as DMA and Interrupt controllers, Timers, Power
Management, System Management, GPIO, RTC, and LPC Configuration Registers.
LPC Interface Configuration Register Details
Address locations that are not listed are considered reserved register locations.
Reserved registers are read only and return all zeros. For more information on the
format of the register description tables that follow in this chapter, see Section 7.1.1,
“Register Description Tables”.
Table 19-1. Bus 0, Device 31, Function 0: Summary of LPC Interface PCI Configuration
Registers (Sheet 1 of 2)
Offset Start Offset End
Register ID - Description
00h
04h
06h
08h
09h
0Dh
0Eh
2Ch
40h
44h
48h
4Ch
60h
61h
62h
63h
64h
68h
69h
6Ah
03h
05h
07h
08h
0Bh
0Dh
0Eh
2Fh
43h
47h
48h
4Ch
60h
61h
62h
63h
64h
68h
69h
6Ah
“Offset 00h: ID: Vendor Identification Register” on page 734
“Offset 04h: CMD: Device Command Register” on page 735
“Offset 06h: STS: Status Register” on page 736
“Offset 08h: RID: Revision ID Register” on page 737
“Offset 09h: CC: Class Code Register” on page 737
“Offset 0Dh: MLT: Master Latency Timer Register” on page 737
“Offset 0Eh: HTYPE: Header Type Register” on page 738
“Offset 2Ch: SID: Subsystem Identifiers Register” on page 738
“Offset 40h: ABASE: ACPI Base Address Register” on page 739
“Offset 44h: ACTL: ACPI Control Register” on page 739
“Offset 48h: GBA: GPIO Base Address Register” on page 740
“Offset 4Ch: GC: GPIO Control Register” on page 741
“Offset 60h: PARC: PIRQA Routing Control Register” on page 741
“Offset 61h: PBRC: PIRQB Routing Control Register” on page 742
“Offset 62h: PCRC: PIRQC Routing Control Register” on page 742
“Offset 63h: PDRC: PIRQDQ Routing Control Register” on page 743
“Offset 64h: SCNT: Serial IRQ Control Register” on page 744
“Offset 68h: PERC: PIRQEQ Routing Control Register” on page 745
“Offset 69h: PFRC: PIRQF Routing Control Register” on page 745
“Offset 6Ah: PGRC: PIRQG Routing Control Register” on page 746
Default
Value
50318086h
0007h
0200h
Variable
060100h
00h
80H
00000000h
00000001h
00h
00000001h
00h
80h
80h
80h
80h
10h
80h
80h
80h
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
733