EP80579 Datasheet, PDF (1521/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.6.30 GORCH – Good Octets Received Count High Register
This is the high 32b of a register that counts the number of octets received which are
associated with good packets (no link or CRC errors, no flow-control packets). This
counter is incremented for each good regular packet received to the Receive Packet
Buffer. Regular packets dropped due to Receive Packet Buffer overruns or due to the
driver's receiver being disabled are not included in this count. {GORCH,GORCL}
together make up a logical 64-bit register. Each half must be accessed independently
using separate 32-bit accesses. Both registers are reset when the upper 32-bit value
(GORCH) is read. The register sticks at 0xFFFF_FFFF_FFFF_FFFF.
Table 37-108.GORCH: Good Octets Received Count High Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 408Ch
Offset End: 408Fh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 408Ch
Offset End: 408Fh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 408Ch
Offset End: 408Fh
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
Bit Description
31 : 00
GORCH
Number of good octets received - upper 4 bytes
Sticky
Bit Reset
Value
0h
Bit Access
RC
37.6.6.31 GOTCL – Good Octets Transmitted Count Low Register
This is the low 32b of a register that counts the number of octets transmitted as good
packets. Good packets are considered those which are 64B or more in length (from
<Destination Address> through <CRC>, inclusively), and do not encounter an error
(collision, etc.) during transmission. This count does not include octets transmitted in
flow control packets. This register will only increment when transmits are enabled by
the driver. Octets from the <Destination Address> field through the <CRC> field are
included in this count. {GOTCH,GOTCL} together make up a logical 64-bit register.
Each half must be accessed independently using separate 32-bit accesses. Both
registers are reset when the upper 32-bit value (GOTCH) is read. The register sticks at
0xFFFF_FFFF_FFFF_FFFF.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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