EP80579 Datasheet, PDF (1739/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
48.4.2
48.4.2.1
Integrated Memory Controller Hub (IMCH)
IMCH Reset
Table 48-7. IMCH Reset Signals
Signal Name
RSTIN#
IO Type
LVTTL,3.3V
Direction
Ball
Count
I
1
External
Pull-Up/
Down
[Ohms]
BSC/
XOR
Signal Description Normal/Alternate Mode
BSC
IMCH Reset Input: This input must be connected
to PLTRST#.
PWRGD
LVTTL,3.3V I
1
TOTAL
2
BSC
IMCH Power Good: Asynchronously resets the
entire IMCH component, including “sticky” bits.
Driven by platform logic to indicate all board
power supplies are valid.
48.4.2.2 DDR2 SDRAM
Table 48-8. DDR2 Interface Signals (Sheet 1 of 2)
Signal Name
DDR_CK[5:0]
DDR_CK[5:0]#
DDR_CS[1:0]#
DDR_RAS#
DDR_CAS#
DDR_WE#
DDR_DM[8:0]
DDR_BA[2:0]
DDR_A[14:0]
DDR_DQ[63:0]
DDR_ECC[7:0]
IO Type
SSTL_18
SSTL_18
SSTL_18
SSTL_18
SSTL_18
SSTL_18
SSTL_18
SSTL_18
SSTL_18
SSTL_18
SSTL_18
Direction
Ball
Count
O
6
O
6
O
2
O
1
O
1
O
1
O
9
O
3
O
15
I/O
64
I/O
8
External
Pull-Up/
Down
[Ohms]
BSC/
XOR
Signal Description Normal/Alternate Mode
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
DDR Channel Command Clock (Differential):
The positive side of the command clocks used by
the DDR DRAMs to latch the DDR_A[14:0],
DDR_BA[2:0], DDR_RAS#, DDR_CAS#,
DDR_WE#, DDR_CKE[1:0], and DDR_CS[1:0]#
signals.
DDR Channel Command Clock (Differential):
The negative side of the differential command
clock (see DDR_CK[5:0]).
DDR Channel Chip Select: Used to indicate to
which DRAM device cycles are targeted.
DDR Channel Row Address Strobe: Used to
indicate a valid row address and open a row
DDR Channel Column Address Strobe: Used to
indicate a valid column address and initiate a
transaction.
DDR Channel Write Enable: Used to indicate a
write cycle.
DDR Channel Data Mask: Data mask for write
data.
DDR Channel Bank Address: The DDR bank
address signals. These signals are outputs of the
IMCH and select which bank within a row is
selected.
DDR Channel Memory Address: The DDR
memory address signals.
DDR Channel Data Bus: The DDR data bus
provides the data to/from the DRAM devices.
DDR Channel ECC Bits: ECC bits for the data on
the interface.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1739